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ISL45041EVAL1Z Fiches technique(PDF) 5 Page - Intersil Corporation

No de pièce ISL45041EVAL1Z
Description  TFT-LCD I2C Programmable VCOM Calibrator
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Fabricant  INTERSIL [Intersil Corporation]
Site Internet  http://www.intersil.com/cda/home
Logo INTERSIL - Intersil Corporation

ISL45041EVAL1Z Fiches technique(HTML) 5 Page - Intersil Corporation

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ISL45041
5
FN6189.5
October 30, 2014
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Application Information
This device provides the ability to reduce the flicker of an LCD
panel by adjustment of the VCOM voltage during production test
and alignment. A 128-step resolution is provided under digital
control, which adjusts the sink current of the output. The output is
connected to an external voltage divider, so that the device will
have the capability to reduce the voltage on the output by
increasing the output sink current.
The adjustment of the output is provided by the 2-wire I2C serial
interface.
Expected Output Voltage
The ISL45041 provides an output sink current, which lowers the
voltage on the external voltage divider (VCOM output voltage).
Equations 1 and 2 can be used to calculate the output current
(IOUT) and output voltage (VOUT) values. The setting is the register
value +1 with a value between 1 and 128.
Table 1 gives the calculated value of VOUT using the resistor values
of: RSET = 24.9kΩ, R1 = 200kΩ, R2 = 243kΩ and AVDD =10V.
RSET Resistor
The external RSET resistor sets the full-scale sink current, ISET
maximum, that determines the lowest voltage of the external
voltage divider R1 and R2 (Figure 2). The voltage difference between
the OUT pin and SET pin (Figure 3), which are also the drain and
source of the output transistor, must be greater than 1.75V. This will
keep the output transistor in its saturation region to maintain linear
operation over the full range of register values. Expected current
settings and 7-bit accuracy occurs when the output MOS transistor is
operating in the saturation region. Figure 3 shows the internal
connection for the output MOS transistor. The value of the AVDD
supply sets the voltage at the source of the output transistor. This
voltage is equal to (Setting/128) x (AVDD/20). The ISET current is
therefore equal to (Setting/128) x (AVDD/20 x RSET). The drain
voltage is calculated using Equation 2. The values of R1 and R2
(Equation 2) should be determined using IOUT maximum (setting
equal to 128) so the minimum value of VOUT is greater than 1.75V +
AVDD/20.
Ramp-Up of the VDD Power Supply
The ramp-up from 10% VDD to 90% VDD level must be achieved
in 10ms or less to ensure that the EEPROM and power-on-reset
circuits are synchronized and the correct value is read from the
EEPROM Memory.
Power Supply Sequence
The recommended power supply sequencing is shown in
Figure 3. When applying power, VDD should be applied before or
at the same time as AVDD. The minimum time for tVS is 0µs.
When removing power, the sequence of VDD and AVDD is not
important.
Do not remove VDD or AVDD within 100ms of the start of the
EEPROM programming cycle. Removing power before the
EEPROM programming cycle is completed may result in
corrupted data in the EEPROM.
TABLE 1.
SETTING VALUE
VOUT
(V)
1
5.468
10
5.313
20
5.141
30
4.969
40
4.797
50
4.625
60
4.453
70
4.281
80
4.109
90
3.936
100
3.764
110
3.592
128
3.282
RSET
FIGURE 2. OUTPUT CONNECTION CIRCUIT EXAMPLE
-
+
ISL45041
SET
OUT
AVDD
R1
R2
AVDD
IOUT
I
OUT
Setting
128
--------------------- x
AV
DD
20 R
SET

---------------------------
=
V
OUT
R
2
R
1
R
2
+
---------------------



AV
DD 1
Setting
128
--------------------- x
R
1
20 R
SET

---------------------------



=
(EQ. 1)
(EQ. 2)
FIGURE 3. OUTPUT CONNECTION CIRCUIT EXAMPLE
AVDD = 15V
RSET
OUT PIN
R1
R2
AVDD
VSAT
SET PIN
SETTING
128
---------------------------- x
AV
DD
20
------------------
0.5V
FIGURE 3. POWER SUPPLY SEQUENCE
VDD
AVDD
tVS


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