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AM3358BGCZA80EP Fiches technique(PDF) 3 Page - Texas Instruments |
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AM3358BGCZA80EP Fiches technique(HTML) 3 Page - Texas Instruments |
3 / 231 page AM3358-EP www.ti.com SLUSC35A – APRIL 2015 – REVISED APRIL 2015 Operation in a Unified Memory Architecture Asymmetric Outputs – LCD Controller – Up to Three 32-Bit Enhanced Quadrature Encoder Pulse (eQEP) Modules • Up to 24-Bit Data Output; 8 Bits per Pixel • Device Identification (RGB) – Contains Electrical Fuse Farm (FuseFarm) of • Resolution up to 2048 × 2048 (With Which Some Bits are Factory Programmable Maximum 126-MHz Pixel Clock) • Production ID • Integrated LCD Interface Display Driver (LIDD) Controller • Device Part Number (Unique JTAG ID) • Integrated Raster Controller • Device Revision (Readable by Host ARM) • Integrated DMA Engine to Pull Data from the • Debug Interface Support External Frame Buffer Without Burdening the – JTAG and cJTAG for ARM (Cortex-A8 and Processor via Interrupts or a Firmware Timer PRCM), PRU-ICSS Debug • 512-Word Deep Internal FIFO – Supports Device Boundary Scan • Supported Display Types: – Supports IEEE 1500 – Character Displays - Uses LIDD • DMA Controller to Program these Displays – On-Chip Enhanced DMA Controller (EDMA) has – Passive Matrix LCD Displays - Uses LCD Three Third-Party Transfer Controllers (TPTCs) Raster Display Controller to Provide and One Third-Party Channel Controller Timing and Data for Constant Graphics (TPCC), Which Supports up to 64 Refresh to a Passive Display Programmable Logical Channels and Eight – Active Matrix LCD Displays - Uses QDMA Channels. EDMA is Used for: External Frame Buffer Space and the • Transfers to and from On-Chip Memories Internal DMA Engine to Drive Streaming • Transfers to and from External Storage Data to the Panel (EMIF, GPMC, Slave Peripherals) – 12-Bit Successive Approximation Register • Inter-Processor Communication (IPC) (SAR) ADC – Integrates Hardware-Based Mailbox for IPC and • 200K Samples per Second Spinlock for Process Synchronization Between • Input can be Selected from any of the Eight Cortex-A8, PRCM, and PRU-ICSS Analog Inputs Multiplexed Through an 8:1 • Mailbox Registers that Generate Interrupts Analog Switch – Initiators (Cortex-A8, PRCM) • Can be Configured to Operate as a 4-Wire, • Spinlock has 128 Software-Assigned Lock 5-Wire, or 8-Wire Resistive Touch Screen Registers Controller (TSC) Interface • Security – Up to Three 32-Bit eCAP Modules – Crypto Hardware Accelerators (AES, SHA, PKA, • Configurable as Three Capture Inputs or RNG) Three Auxiliary PWM Outputs • Boot Modes – Up to Three Enhanced High-Resolution PWM – Boot Mode is Selected via Boot Configuration Modules (eHRPWMs) Pins Latched on the Rising Edge of the • Dedicated 16-Bit Time-Base Counter With PWRONRSTn Reset Input Pin Time and Frequency Controls • Package: • Configurable as Six Single-Ended, Six Dual- – 324-Pin S-PBGA-N324 Package Edge Symmetric, or Three Dual-Edge (GCZ Suffix), 0.80-mm Ball Pitch 1.2 Applications Supports Defense, Aerospace, and Medical • Extended Product Life Cycle Applications: • Extended Product Change Notification • Controlled Baseline • Product Traceability • One Assembly and Test Site • One Fabrication Site • Available in –40°C to 105°C Temperature Range Copyright © 2015, Texas Instruments Incorporated Device Summary 3 Submit Documentation Feedback Product Folder Links: AM3358-EP |
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