Moteur de recherche de fiches techniques de composants électroniques |
|
CSD95379Q3M Fiches technique(PDF) 11 Page - Texas Instruments |
|
|
CSD95379Q3M Fiches technique(HTML) 11 Page - Texas Instruments |
11 / 22 page VO Vin PWM VDD VDD SKIP# PWM GND BST DRVH LL DRVL HSgate Vsw LSgate VIN VSW PGND A Gate Drive Current (IDD) V Gate Drive Voltage (VDD) V Input Voltage (VIN) V Averaged Switched Node Voltage (VSW_AVG) A Output Current (IOUT) Averaging Circuit Control FET Sync FET A Input Current (IIN) CSD95379Q3M LO Boot Boot_R CBoot Cin Co SKIP# CSD95379Q3M www.ti.com SLPS446C – APRIL 2014 – REVISED NOVEMBER 2014 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information The Power Stage CSD95379Q3M is a highly optimized design for synchronous buck applications using NexFET devices with a 5 V gate drive. The control FET and sync FET silicon are parametrically tuned to yield the lowest power loss and highest system efficiency. As a result, a rating method is used that is tailored towards a more systems centric environment. The high-performance gate driver IC integrated in the package helps minimize the parasitics and results in extremely fast switching of the power MOSFETs. System level performance curves such as Power Loss, Safe Operating Area, and normalized graphs allow engineers to predict the product performance in the actual application. 8.1.1 Power Loss Curves MOSFET-centric parameters such as RDS(ON) and Qgd are primarily needed by engineers to estimate the loss generated by the devices. In an effort to simplify the design process for engineers, TI has provided measured power loss performance curves. Figure 1 plots the power loss of the CSD95379Q3M as a function of load current. This curve is measured by configuring and running the CSD95379Q3M as it would be in the final application (see Figure 12). The measured power loss is the CSD95379Q3M device power loss which consists of both input conversion loss and gate drive loss. Equation 1 is used to generate the power loss curve. Power Loss = (VIN × IIN) + (VDD × IDD) – (VSW_AVG × IOUT) (1) The power loss curve in Figure 1 is measured at the maximum recommended junction temperature of TJ = 125°C under isothermal test conditions. Figure 12. Power Loss Test Circuit 8.1.2 Safe Operating Curves (SOA) The SOA curves in the CSD95379Q3M data sheet give engineers guidance on the temperature boundaries within an operating system by incorporating the thermal resistance and system power loss. Figure 3 and Figure 4 outline the temperature and airflow conditions required for a given load current. The area under the curve dictates the safe operating area. All the curves are based on measurements made on a PCB design with dimensions of 4 inches (W) × 3.5 inches (L) × 0.062 inch (T) and 6 copper layers of 1 oz. copper thickness. Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Links: CSD95379Q3M |
Numéro de pièce similaire - CSD95379Q3M |
|
Description similaire - CSD95379Q3M |
|
|
Lien URL |
Politique de confidentialité |
ALLDATASHEET.FR |
ALLDATASHEET vous a-t-il été utile ? [ DONATE ] |
À propos de Alldatasheet | Publicité | Contactez-nous | Politique de confidentialité | Echange de liens | Fabricants All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |