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MAX6958 Fiches technique(PDF) 3 Page - Maxim Integrated Products

No de pièce MAX6958
Description  2-Wire Interfaced, 3V to 5.5V, 4-Digit, 9-Segment LED Display Drivers with Keyscan
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Fabricant  MAXIM [Maxim Integrated Products]
Site Internet  https://www.maximintegrated.com/en.html
Logo MAXIM - Maxim Integrated Products

MAX6958 Fiches technique(HTML) 3 Page - Maxim Integrated Products

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2-Wire Interfaced, 3V to 5.5V, 4-Digit,
9-Segment LED Display Drivers with Keyscan
_______________________________________________________________________________________
3
Note 1: All parameters tested at TA =+25°C. Specifications over temperature are guaranteed by design.
Note 2: Guaranteed by design.
Note 3: A master device must provide a hold time of at least 300ns for the SDA signal (referred to VIL of the SCL signal) in order to
bridge the undefined region of SCL’s falling edge.
Note 4: CB = total capacitance of one bus line in pF. tR and tF measured between 0.3V+ and 0.7V+.
Note 5: ISINK
≤ 6mA. CB = total capacitance of one bus line in pF. tR and tF measured between 0.3V+ and 0.7V+.
Note 6: Input filters on the SDA and SCL inputs suppress noise spikes less than 50ns.
DC ELECTRICAL CHARACTERISTICS (continued)
(V+ = 3V to 5.5V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at V+ = 5V, TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Pullup to V+ INPUT1, INPUT2
IPULLUP
26.5
µA
ISINK = 6mA, TA = -40
°C to +85°C
0.4
IRQ/SEG9, SDA Output Low
Voltage
VOLBK
ISINK = 4mA, TA = TMIN to TMAX
0.4
V
SDA Output Low Voltage
VOL(SDA)
ISINK = 6mA
0.4
V
TIMING CHARACTERISTICS
(V+ = 3V to 5.5V, TA = TMIN to TMAX, Figure 1, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Serial Clock Frequency
fSCL
400
kHz
Bus Free Time Between a STOP
and a START Condition
tBUF
1.3
µs
Hold Time (Repeated) START
Condition
tHD, STA
0.6
µs
Repeated START Setup Time
tSU, STA
0.6
µs
STOP Condition Setup Time
tSU, STO
0.6
µs
Data Hold Time
tHD, DAT
(Note 3)
0.9
µs
Data Setup Time
tSU, DAT
100
ns
SCL Clock Low Period
tLOW
1.3
µs
SCL Clock High Period
tHIGH
0.6
µs
Rise Time of Both SDA and SCL
Signals, Receiving
tR
(Notes 2, 4)
20 +
0.1CB
300
ns
Fall Time of Both SDA and SCL
Signals, Receiving
tF
(Notes 2, 4)
20 +
0.1CB
300
ns
Fall Time of SDA Transmitting
tF
(Notes 2, 5)
20 +
0.1CB
250
ns
Pulse Width of Spike Suppressed
tSP
(Note 6)
50
ns
Capacitive Load for Each Bus
Line
CB
400
pF


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