Low-Power, Serial, 14-Bit DACs

with Force/Sense Voltage Output

_______________________________________________________________________________________

5

Note 1: INL guaranteed between codes 64 and 16383.

Note 2: Offset is measured at the code that comes closest to 10mV.

Note 5: INL guaranteed between codes 128 and 16383.

ELECTRICAL CHARACTERISTICS—MAX5173 (continued)

µA

110

Shutdown Current (Note 4)

ns

150

SCLK Clock Period

ns

75

SCLK Pulse Width High

ns

75

CONDITIONS

SCLK Pulse Width Low

ns

60

CS Fall to SCLK Rise Setup

Time

ns

0

SCLK Rise to CS Rise Hold

Time

ns

60

SDI Setup Time

ns

0

SDI Hold Time

ns

200

SCLK Rise to DOUT Valid

Propagation Delay

ns

75

CS Rise to SCLK Rise Hold Time

ns

200

SCLK Fall to DOUT Valid

Propagation Delay

To ±0.5LSB, from 10mV to full-scale

µs

12

Output Settling Time

ns

10

SCLK Rise to CS Fall Delay

ns

150

CS Pulse Width High

V/µs

0.6

SR

Voltage Output Slew Rate

V

0

Output Voltage Swing (Note 3)

µA

-0.1

0

0.1

Current into FB

µs

40

Time Required to Exit Shutdown

UNITS

MIN

TYP

MAX

SYMBOL

PARAMETER

nV-s

1

Digital Feedthrough

V

2.7

3.6

Positive Supply Voltage

mA

0.26

0.35

Power-Supply Current (Note 4)

DYNAMIC PERFORMANCE

POWER SUPPLIES

TIMING CHARACTERISTICS