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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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OPA625 Fiches technique(PDF) 31 Page - Texas Instruments |
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OPA625 Fiches technique(HTML) 31 Page - Texas Instruments |
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31 / 44 page  Frequency (kHz) -175 -150 -125 -100 -75 -50 -25 0 0 50 100 150 200 250 300 350 400 450 500 -115.91 dBc (Third Harmonic) THD = -110.8 dBc SNR = 91.88 dB SINAD = 91.86 dB ENOB = 14.97 FLT SH C 15 C J K OPA625, OPA2625 www.ti.com SBOS688 – APRIL 2015 Typical Applications (continued) The SAR ADC inputs and sampling capacitors must be driven by the OPA625 to 16-bit levels within the acquisition time of the ADC. For the example illustrated in Figure 72, the OPA625 is used to drive the ADS8860 at a sample rate of 1 MSPS. 9.2.1.2 Detailed Design Procedure The circuit illustrated in Figure 72 consists of the SAR ADC driver, a low-pass filter and the SAR ADC. The SAR ADC driver circuit consists of an OPA625 configured in an inverting gain of 1. The filter consists of RFLT and CFLT, connected between the output of the OPA625 and input of the ADS8860. Selecting the proper values for each of these passive components is critical to obtain the best performance from the ADC. Capacitor CFLT serves as a charge reservoir, providing the necessary charge to the ADC sampling capacitors. The dynamic load presented by the ADC creates a glitch on the filter capacitor, CFLT. To minimize the magnitude of this glitch, choose a value for CFLT large enough to maintain a glitch amplitude of less than 100 mV. Maintaining such a low glitch amplitude at the amplifier output makes sure that the amplifier remains in the linear operating region, and results in a minimum settling time. Using Equation 6, a 10-nF capacitor is selected for CFLT. (6) Connecting a 10-nF capacitor directly to the output of the OPA625 degrades the OPA625 phase margin and results in stability and settling-time problems. To properly drive the 10-nF capacitor, use a series resistor (RFLT) to isolate the capacitor, CFLT, from the OPA625. RFLT must be sized based upon several constraints. To determination a suitable value for RFLT, consider the impact upon the THD due to the voltage divider effect from RFLT reacting with the switch resistance (RSW) of the ADC input circuit, as well as the impact of the output impedance upon amplifier stability. In this example, 4.7- Ω resistors are selected. In this design example, Figure 16 can be used to estimate a suitable value for RISO. RISO represents the total resistance in series with CFLT, and in this example is equivalent to 2 × RFLT. For step-by-step design procedure, circuit schematics, bill of materials, printed circuit board (PCB) files, simulation results, and test results, refer to TI Precision Design, TIDU014, "Power-optimized 16-bit 1MSPS Data Acquisition Block for Lowest Distortion and Noise Reference Design". 9.2.1.3 Application Curves Figure 74 illustrates the performance of the circuit shown in Figure 72. 4096-point FFT at 1 MSPS, fIN = 10 kHz , VIN = 1.5 VRMS Figure 74. ADC Output FFT for Figure 72 Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback 31 Product Folder Links: OPA625 OPA2625 |
Numéro de pièce similaire - OPA625 |
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Description similaire - OPA625 |
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