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74ALVT16827 Fiches technique(PDF) 1 Page - NXP Semiconductors |
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74ALVT16827 Fiches technique(HTML) 1 Page - NXP Semiconductors |
1 / 16 page 1. General description The 74ALVT16827 high-performance BiCMOS device combines low static and dynamic power dissipation with high speed and high output drive. It is designed for VCC operation at 2.5 V or 3.3 V with I/O compatibility to 5 V. The 74ALVT16827 20-bit buffers provide high performance bus interface buffering for wide data/address paths or buses carrying parity. They have NOR Output Enables (nOE1 and nOE2) for maximum control flexibility. 2. Features s Multiple VCC and GND pins minimize switching noise s 5 V I/O compatible s Live insertion and extraction permitted s 3-state output buffers s Power-up 3-state s Output capability: +64 mA and −32 mA s Latch-up protection: x JESD 78 exceeds 500 mA s ElectroStatic Discharge (ESD) protection: x MIL STD 883 Method 3015: exceeds 2000 V x Machine model: exceeds 200 V s Bus hold data inputs eliminate need for external pull-up resistors to hold unused inputs 3. Quick reference data 74ALVT16827 20-bit buffer/line driver; non-inverting; 3-state Rev. 03 — 2 June 2005 Product data sheet Table 1: Quick reference data GND = 0 V; Tamb = 25 °C. Symbol Parameter Conditions Min Typ Max Unit tPLH propagation delay nAx to nYx CL = 50 pF; VCC = 2.5 V 1.0 2.0 2.9 ns CL = 50 pF; VCC = 3.3 V 0.7 1.5 2.2 ns tPHL propagation delay nAx to nYx CL = 50 pF; VCC = 2.5 V 1.0 2.0 3.0 ns CL = 50 pF; VCC = 3.3 V 0.8 1.6 2.3 ns CI input capacitance on DIR, OE VI = 0 V or VCC -3 -pF |
Numéro de pièce similaire - 74ALVT16827_15 |
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Description similaire - 74ALVT16827_15 |
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