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M34250M2 Fiches technique(PDF) 17 Page - Mitsubishi Electric Semiconductor |
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M34250M2 Fiches technique(HTML) 17 Page - Mitsubishi Electric Semiconductor |
17 / 58 page MITSUBISHI ELECTRIC 17 MITSUBISHI MICROCOMPUTERS 4250 Group SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER (6) Control register related to interrupt • Timer control register V1 Interrupt enable bits of external and timer 1 are assigned to register V1. Set the contents of this register through register A with the TV1A instruction. The TAV1 instruction can be used to transfer the contents of register V1 to register A. (7) Interrupt sequence Interrupts occur only when the respective INTE flag, interrupt enable bits (V10, V11), and interrupt request flags (EXF0, T1F) are “1.” The interrupt actually occurs 2 to 3 machine cycles after the cycle in which all three conditions are satisfied. The interrupt occurs after 3 machine cycles only when the three interrupt conditions are satisfied on execution of other than one-cycle instructions (Refer to Figure 16). Fig. 16 Interrupt sequence Table 6 Control register related to interrupt V13 V12 V11 V10 Timer control register V1 G1/TOUT pin function selection bit Prescaler/timer 1 operation start bit Timer 1 interrupt enable bit External interrupt enable bit Port G1 (I/O) TOUT pin (output)/port G1(input) Prescaler stop (initial state) / timer 1 stop (state retained) Prescaler / timer 1 operation Interrupt disabled (SNZ1 instruction is valid) Interrupt enabled (SNZ1 instruction is invalid) Interrupt disabled (SNZ0 instruction is valid) Interrupt enabled (SNZ0 instruction is invalid) 0 1 0 1 0 1 0 1 Note: “R” represents read enabled, and “W” represents write enabled. at reset : 00002 R/W at RAM back-up : 00002 T1 T2 T3 T4 T1 T2 T3 T4 T1 T2 T3 T4 T1 T2 T3 T4 T1 T2 T3 T4 2 to 3 machine cycles (Notes 1, 2) Software starts from the interrupt address. Flag cleared Interrupt enabled state. q When an interrupt request flag is set after its interrupt is enabled f (XIN) EI instruction execution cycle Interrupt enable flag (INTE) Retaining level for 5 cycles or more of f(XIN) is necessary. Interrupt disabled state. EXF0 flag T1F flag G0/INT pin External interrupt Timer 1 interrupt Interrupt activated condition is satisfied. 1 machine cycle The address is stacked to the last cycle. This interval of cycles depends on the executed instruction at the time when each interrupt activated condition is satisfied. Notes 1: 2: |
Numéro de pièce similaire - M34250M2 |
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Description similaire - M34250M2 |
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