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M32000D3FP Fiches technique(PDF) 7 Page - Mitsubishi Electric Semiconductor |
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M32000D3FP Fiches technique(HTML) 7 Page - Mitsubishi Electric Semiconductor |
7 / 45 page SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS M32000D3FP 7 PIN DESCRIPTION (2/3) type pin name name I/O function bus SID space I/O Space identifier between user space and I/O space. control identifier (Hi-z)* SID = "L": user space SID = "H": I/O space SID is bidirectional. When accessing the internal DRAM from outside the M32000D3FP while the M32000D3FP is in the hold state, input an "L" level from the system bus side. ____ ____ BCH, BCL byte control I/O Indicates the valid byte positions of transferred data. (Hi-z)* ____ ____ BCH corresponds to the MSB side (D0 to D7), and BCL corresponds ____ to the LSB side (D8 to D15). During a read bus cycle, both BCH ____ and BCL are an "L" level. ____ ____ During a write bus cycle, either BCH and/or BCL is an "L" level depending on the byte(s) to be written. When accessing the internal DRAM from an external bus master, the byte control signal is input from the system bus side. __ BS bus start output __ When the M32000D3FP drives an external bus cycle, BS goes to an "L" level at the start of the bus cycle. __ In burst transfer, BS goes to the "L" level for each transfer cycle. When accessing internal resources such as an internal __ DRAM or internal I/O register, BS is not output. ST bus status output Indicates whether the bus cycle that the M32000D3FP drives is an instruction fetch access cycle or an operand access cycle. ST = "L": for instruction fetch access ST = "H": for operand access ST = undefined: when idle __ R/W read/write I/O __ Outputs R/W to identify whether the external bus cycle a read or a write cycle. When accessing the internal DRAM from an external __ bus master, R/W is input from the external bus. ______ BURST burst output The M32000D3FP drives two consecutive bus cycles to access 32-bit data allocated on the 32-bit word boundary. For instruction fetches, it drives 8 (max.) consecutive cycles (8 cycles in instruction cache mode) to data on the 128-bit boundary. ______ During these consecutive bus cycles, BURST goes to "L" level. When accessing 32-bit data, an "L" level followed by an "H" level is output from address A30, because the MSB-side 16 bits are accessed prior to the LSB-side 16 bits. When accessing 128-bit data, the addresses are output from an arbitrary 16-bit aligned address and wraparound within a 128-bit aligned boundary. * (Hi-z): This pin goes to high-impedance in the hold state. (Hi-z)* (Hi-z)* (Hi-z)* (Hi-z)* |
Numéro de pièce similaire - M32000D3FP |
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Description similaire - M32000D3FP |
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