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M306V0ME Fiches technique(PDF) 62 Page - Mitsubishi Electric Semiconductor |
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M306V0ME Fiches technique(HTML) 62 Page - Mitsubishi Electric Semiconductor |
62 / 256 page M306V0ME-XXXFP M306V0EEFP MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER 62 Rev. 1.0 Figure 2.7.8 Hardware interrupts priorities ________ Reset > DBC > Watchdog timer > Peripheral I/O > Single step > Address match Figure 2.7.9 Maskable interrupts priorities (peripheral I/O interrupts) VSYNC UART0 reception UART2 reception/ACK A-D conversion DMA1 Bus collision detection Timer A0 Data slicer UART0 transmission UART2 transmission/NACK Priority of peripheral I/O interrupts (if priority levels are same) OSD2 Timer B2 Timer B0 Timer A3 Timer A1 Timer B1 Timer A4 Timer A2 INT1 INT0 Level 0 (initial value) Priority level of each interrupt High OSD1 DMA0 Processor interrupt priority level (IPL) Interrupt enable flag (I flag) Watchdog timer Reset DBC Interrupt request accepted Low Address match |
Numéro de pièce similaire - M306V0ME |
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Description similaire - M306V0ME |
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