Moteur de recherche de fiches techniques de composants électroniques |
|
M306V0ME Fiches technique(PDF) 43 Page - Mitsubishi Electric Semiconductor |
|
M306V0ME Fiches technique(HTML) 43 Page - Mitsubishi Electric Semiconductor |
43 / 256 page M306V0ME-XXXFP M306V0EEFP MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER 43 Rev. 1.0 01000 Invalid Division by 2 mode 10000 Invalid Division by 4 mode Invalid Invalid 0 1 0 Invalid Division by 8 mode 11000 Invalid Division by 16 mode 00000 Invalid No-division mode Invalid Invalid 1 Invalid 0 1 Low-speed mode Invalid Invalid 1 Invalid 1 1 Low power dissipation mode 2.5.7 Status Transition of BCLK Power dissipation can be reduced and low-voltage operation achieved by changing the count source for internal clock φ. Table 2.5.4 shows the operating modes corresponding to the settings of system clock control registers 0 and 1. After a reset, operation defaults to division by 8 mode. When shifting to stop mode, the main clock division select bit 0 (bit 6 at address 000616) is set to “1”. The following shows the operational modes of internal clock φ. (1) Division by 2 mode The main clock is divided by 2 to obtain the BCLK. (2) Division by 4 mode The main clock is divided by 4 to obtain the BCLK. (3) Division by 8 mode The main clock is divided by 8 to obtain the BCLK. Note that oscillation of the main clock must have stabilized before transferring from this mode to another mode. (4) Division by 16 mode The main clock is divided by 16 to obtain the BCLK. (5) No-division mode The main clock is used as the BCLK. (6) Low-speed mode fC is used as the BCLK. Note that oscillation of both the main and sub clocks must have stabilized before transferring from this mode to another or vice versa. At least 2 to 3 seconds are required after the sub clock starts. Therefore, the program must be written to wait until this clock has stabilized immediately after powering up and after stop mode is cancelled. (7) Low power dissipation mode fC is the BCLK and the main clock is stopped. Note: When switching the count source for BCLK between XIN and XCIN it needs that the oscillation of the switched count source is sufficiently stable. Shift after taking the oscillation stabilizing time by software. CM17 CM16 CM07 CM06 CM05 CM04 Operating mode of BCLK Table 2.5.4 Operating modes dictated by settings of system clock control registers 0 and 1 |
Numéro de pièce similaire - M306V0ME |
|
Description similaire - M306V0ME |
|
|
Lien URL |
Politique de confidentialité |
ALLDATASHEET.FR |
ALLDATASHEET vous a-t-il été utile ? [ DONATE ] |
À propos de Alldatasheet | Publicité | Contactez-nous | Politique de confidentialité | Echange de liens | Fabricants All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |