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LF9502JC25 Fiches technique(PDF) 1 Page - LOGIC Devices Incorporated |
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LF9502JC25 Fiches technique(HTML) 1 Page - LOGIC Devices Incorporated |
1 / 7 page DEVICES INCORPORATED 1 LF9502 2K Programmable Line Buffer 08/16/2000–LDS.9502-G Video Imaging Products u u u u u 50 MHz Maximum Operating Frequency u u u u u Programmable Buffer Length from 2 to 2049 Clock Cycles u u u u u 10-bit Data Inputs and Outputs u u u u u Data Delay and Data Recirculation Modes u u u u u Supports Positive or Negative Edge System Clocks u u u u u Expandable Data Word Width or Buffer Length u u u u u 44-pin PLCC, J-Lead FEATURES DESCRIPTION LF9502 2K Programmable Line Buffer DEVICES INCORPORATED The LF9502 is a high-speed, 10-bit programmable line buffer. Some applications the LF9502 is useful for include sample rate conversion, data time compression/expansion, soft- ware controlled data alignment, and programmable serial data shifting. By using the MODSEL pin, two different modes of operation can be selected: delay mode and data recirculation mode. The delay mode provides a minimum of 2 to a maximum of 2049 clock cycles of delay between the input and output of the device. The data recirculation mode provides a feedback path from the data output to the data input for use as a program- mable circular buffer. By using the length control input (LC10-0) and the length control enable (LCEN) the length of the delay buffer or amount of recirculation delay can be programmed. Providing a delay value on the LC10-0 inputs and driving LCEN LOW will load the delay value into the length control register on the next selected clock edge. Two regis- ters, one preceeding the program- mable delay RAM and one following, are included in the delay path. There- fore, the programmed delay value should equal the desired delay minus 2. This consequently means that the value loaded into the length control register must range from 0 to 2047 (to provide an overall range of 2 to 2049). The active edge of the clock input, either positive or negative edge, can be selected with the clock select (CLKSEL) input. All timing is based on the active clock edge selected by CLKSEL. Data can be held tempo- rarily by using the clock enable (CLKEN) input. LF9502 BLOCK DIAGRAM DI9-0 10 10 10 10 10 10 10 MODSEL CLKSEL CLKEN CLK OE REGISTER LCO10-0 LCEN 11 11 TO ALL REGISTERS REGISTER DO9-0 |
Numéro de pièce similaire - LF9502JC25 |
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Description similaire - LF9502JC25 |
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