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LTC1650 Fiches technique(PDF) 4 Page - Linear Technology

No de pièce LTC1650
Description  Low Glitch 16-Bit Voltage Output DAC
Download  12 Pages
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Fabricant  LINER [Linear Technology]
Site Internet  http://www.linear.com
Logo LINER - Linear Technology

LTC1650 Fiches technique(HTML) 4 Page - Linear Technology

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LTC1650
ELECTRICAL CHARACTERISTICS
AVDD = 4.75V to 5.25V, AVSS = – 4.75V to – 5.25V, DVDD = 4.75V to 5.25V, REFLO = 0V, REFHI = 4.096V, VOUT unloaded,
TA = TMIN to TMAX unless otherwise noted.
Note 4: To
±1LSB. Unipolar mode. DAC switched between all 1s and all 0s.
Note 5: Digital Inputs at 0V or DVDD.
Note 6: Measured at VOUT. REFHI = REFLO = 0V, unipolar mode.
Note 7: When part powers up or when it is reset, the output is connected
to VRST through this switch.
Note 8: Reset is active when any supply goes below this threshold.
Note 9: REFLO = 0V, REFHI = VREF. For REFLO ≠ 0V see Operation section.
The q denotes specifications which apply over the full operating
temperature range.
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: Nonlinearity is defined from code 0 to code 65535 (full scale)
(end point INL, see Definitions section).
Note 3: Guaranteed by design. Not subject to test.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Digital I/O Characteristics
VIH
Digital Input High Voltage
q
2.4
V
VIL
Digital Input Low Voltage
q
0.8
V
VOH
Digital Output High Voltage
IOUT = –1mA, DOUT Only
q
VCC – 1.0
V
VOL
Digital Output Low Voltage
IOUT = 1mA, DOUT Only
q
0.4
V
ILK
Digital Input Leakage
VIN = GND to VCC
q
±10
µA
CIN
Digital Input Capacitance
(Note 3)
10
pF
Reset Characteristics
RON
VOUT and VRST Switch Resistance
VRST = 0.5V (Note 7)
q
200
500
Threshold Voltage for Reset
AVDD or DVDD (Note 8)
q
1.5
2.5
3.2
V
AVSS(Note 8)
q
1.5
2.5
3.2
V
Switching Characteristics
t1
DIN Valid to CLK Setup
q
40
ns
t2
DIN Valid to CLK Hold
q
0ns
t3
CLK High Time
(Note 3)
q
40
ns
t4
CLK Low Time
(Note 3)
q
40
ns
t5
CS/LD Pulse Width
(Note 3)
q
50
ns
t6
LSB CLK to CS/LD
(Note 3)
q
40
ns
t7
CS/LD Low to CLK
(Note 3)
q
20
ns
t8
DOUT Output Delay
CLOAD = 100pF
q
5
45
150
ns
t9
CLK Low to CS/LD Low
(Note 3)
q
20
ns
t10
CLR Pulse Width
q
50
ns


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