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LTC1477 Fiches technique(PDF) 4 Page - Linear Technology |
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LTC1477 Fiches technique(HTML) 4 Page - Linear Technology |
4 / 8 page 4 LTC1477/LTC1478 LTC1477 EN (Pin 4): The enable input is a high impedance CMOS gate with an ESD protection diode to ground and should not be forced below ground. This input has about 100mV of built-in hysteresis to ensure clean switching. VINS, VIN1 (Pins 3,2): The VINS supply pin must always be connected to the VIN1 supply pin (see Block Diagram). The VINS supply pin provides power for the input control logic, the current limit and thermal shutdown circuitry; plus provides a sense connection to the input power supply. The gate of the NMOS switch is powered by a charge pump from the VINS supply pin (see Block Diagram). The VIN1 supply pin provides connection to the drain of 1/2 of the output power device. VIN2, VIN3 (Pins 7,6): The VIN2 and VIN3 supply pins are typically tied to the VINS and VIN1 supply pins for lowest ON resistance; i.e., when all four VIN pins are connected together the entire power device is connected (see Block Diagram). Each auxiliary supply pin, VIN2 and VIN3, is connected to the drain of 1/4 of the power device. The VIN2 and VIN3 pins can be selectively disconnected to reduce the short-circuit current limit at the expense of higher RDS(ON). (See Applications Information section for more details.) VOUT (Pins 1,8): The output pins of the LTC1477 must always be tied together. The output is protected against accidental short circuits to ground by a current limit circuit which protects the system power supply and load against damage. A second level of protection is provided by thermal shutdown circuitry which limits the die tempera- ture to 130 °C. LTC1478 AEN, BEN (Pins 4,12): The enable inputs are high imped- ance CMOS gates with ESD protection diodes to ground and should not be forced below ground. These inputs have about 100mV of built-in hysteresis to ensure clean switching. AVINS, AVIN1, BVINS, BVIN1 (Pins 3,2; 11,10): The AVINS or BVINS supply pin must always be connected to the AVIN1 or BVIN1 supply pin (see Block Diagram). The AVINS and BVINS supply pins provide power for the input control logic, the current limit and thermal shutdown circuitry; plus, provides a sense connection to the input power supply. The gate of the NMOS switch is powered by a charge pump from the AVINS and BVINS supply pins (see Block Diagram). The AVIN1 and BVIN1 supply pins provide connection to the drain of 1/2 of the output power device. AVIN2, AVIN3, BVIN2, BVIN3, (Pins 15,14; 7,6): The AVIN2, AVIN3, BVIN2 and BVIN3 supply pins are typically tied to the AVINS, AVIN1, BVINS and BVIN1 supply pins for lowest ON resistance; i.e., when all four AVIN, BVIN pins are con- nected together the entire power device is connected (see Block Diagram). Each auxiliary supply pin, AVIN2, AVIN3, BVIN2 and BVIN3, is connected to the drain of approxi- mately 1/4 of the corresponding power device. The AVIN2, AVIN3, BVIN2 and BVIN3 pins can be selectively discon- nected to reduce the short-circuit current limit at the expense of higher RDS(ON). (See Applications Information section for more details.) AVOUT,BVOUT(Pins1,16;8,9):TheoutputsoftheLTC1478 are protected against accidental short circuits to ground by a current limit circuit which protects the system power supplies and loads against damage. A second level of protection is provided by thermal shutdown circuitry which limits the die temperature to approximately 130 °C. PIN FUNCTIONS |
Numéro de pièce similaire - LTC1477 |
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Description similaire - LTC1477 |
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