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MX25R4035F Fiches technique(PDF) 10 Page - Macronix International |
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MX25R4035F Fiches technique(HTML) 10 Page - Macronix International |
10 / 88 page 10 ADVANCED INFORMATION REV. 0.01, MAR. 06, 2015 MX25R4035F P/N: PM2222 6. DATA PROTECTION During power transition, there may be some false system level signals which result in inadvertent erasure or programming. The device is designed to protect itself from these accidental write cycles. The state machine will be reset as standby mode automatically during power up. In addition, the control register architecture of the device constrains that the memory contents can only be changed after specific command sequences have completed successfully. In the following, there are several features to protect the system from the accidental write cycles during VCC power- up and power-down or from system noise. • Power-on reset: to avoid sudden power switch by system power supply transition, the power-on reset may protect the Flash. • Valid command length checking: The command length will be checked whether it is at byte base and completed on byte boundary. • Write Enable (WREN) command: WREN command is required to set the Write Enable Latch bit (WEL) before issuing other commands to change data. • Deep Power Down Mode: By entering deep power down mode, the flash device is under protected from writing all commands except toggling the CS#. For more detail please see "9-25. Deep Power-down (DP)". • Advanced Security Features: there are some protection and security features which protect content from inadvertent write and hostile access. I. Block lock protection - The Software Protected Mode (SPM) use (BP3, BP2, BP1, BP0) bits to allow part of memory to be protected as read only. The protected area definition is shown as "Table 2. Protected Area Sizes", the protected areas are more flexible which may protect various area by setting value of BP0-BP3 bits. - The Hardware Proteced Mode (HPM) use WP#/SIO2 to protect the (BP3, BP2, BP1, BP0) bits and Status Register Write Protect (SRWD) bit. If the system goes into four I/O mode, the feature of HPM will be disabled. |
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