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IRU1015 Fiches technique(PDF) 5 Page - International Rectifier

No de pièce IRU1015
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IRU1015 Fiches technique(HTML) 5 Page - International Rectifier

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Rev. 1.1
shows the steps in selecting the proper regulator heat
sink for an AMD 486DX4-120 MHz processor.
Assuming the following specifications:
The steps for selecting a proper heat sink to keep the
junction temperature below 135
°C is given as:
1) Calculate the maximum power dissipation using:
2) Select a package from the regulator data sheet and
record its junction to case (or Tab) thermal resistance.
Selecting TO-220 package gives us:
3) Assuming that the heat sink is black anodized, cal-
culate the maximum Heat sink temperature allowed:
θcs=0.05°C/W (heat-sink-to-case thermal
resistance for black anodized)
4) With the maximum heat sink temperature calculated
in the previous step, the heat-sink-to-air thermal re-
sistance (
θSA) is calculated by first calculating the
temperature rise above the ambient as follows:
5) Next, a heat sink with lower
θsa than the one calcu-
lated in step 4 must be selected. One way to do this
is to simply look at the graphs of the "Heat Sink Temp
Rise Above the Ambient" vs. the "Power Dissipation"
and select a heat sink that results in lower tempera-
ture rise than the one calculated in the previous step.
The following heat sinks from AAVID and Thermalloy
meet this criteria.
Note: For further information regarding the above com-
panies and their latest product offerings and application
support contact your local representative or the num-
bers listed below:
AAVID...............PH# (603) 528 3400
Thermalloy.........PH# (214) 243-4321
Designing for Microprocessor Applications
As it was mentioned before the IRU1015 is designed
specifically to provide power for the new generation of
the low voltage processors requiring voltages in the range
of 2.5V to 3.6V generated by stepping down the 5V
supply. These processors demand a fast regulator that
supports their large load current changes. The worst case
current step seen by the regulator is anywhere in the
range of 1 to 7A with the slew rate of 300 to 500ns which
could happen when the processor transitions from “Stop
Clock” mode to the “Full Active” mode. The load current
step at the processor is actually much faster, in the or-
der of 15 to 20ns, however, the de-coupling capacitors
placed in the cavity of the processor socket handle this
transition until the regulator responds to the load current
levels. Because of this requirement the selection of high
frequency low ESR and low ESL output capacitor is
imperative in the design of these regulator circuits.
Figure 5 shows the effects of a fast transient on the
output voltage of the regulator. As shown in this figure,
the ESR of the output capacitor produces an instanta-
neous drop equal to the (
∆VESR=ESR*∆I) and the ESL
effect will be equal to the rate of change of the output
current times the inductance of the capacitor (
∆I/∆t). The output capacitance effect is a droop in
the output voltage proportional to the time it takes for
the regulator to respond to the change in the current,
∆VC = ∆t * ∆I / C ) where ∆t is the response time of the
Air Flow (LFM)
No HS Required
No HS Required
TS = TJ - PD × (θJC + θCS)
TS = 135 - 1.86 × (2.7 + 0.05) = 129!C
PD = 1.2 × (5 - 3.45) = 1.86W
VIN = 5V
VOUT = 3.45V
IOUT(MAX) = 1.2A
TA = 35!C
θJC = 2.7!C/W
θSA =
= 50!C/W
∆T = TS - TA = 129 - 35 = 94!C
∆T = Temperature Rise Above Ambient

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