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UPC8158K Fiches technique(PDF) 5 Page - NEC |
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UPC8158K Fiches technique(HTML) 5 Page - NEC |
5 / 12 page Preliminary Data Sheet P13831EJ1V1DS00 5 µµµµPC8158K ELECTRICAL CHARACTERISTICS Conditions (Unless otherwise specified): TA = +25 °C, VCC1 = VCC2 = VCC3 = 3.0 V, VPS/VAGC = 2.5 V, I/Q (DC) = Ib/Qb (DC) = VCC/2 = 1.5 V, VI/Ibin = VQ/Qbin = 500 mVP-P (each), fI/Qin = 2.625 kHz, π/4DQPSK wave input, transmission rate 42 kbps, filter roll-off α = 0.5, Modulation Pattern: <0000> fLO1in = 178.05 MHz, PLO1in = –15 dBm fLO2in = 1619.05 MHz, PLO2in = –15 dBm fRFout = 1441 MHz – fI/Qin Parameter Symbol Test Conditions MIN. TYP. MAX. Unit UP-CONVERTER + QUADRATURE MODULATOR TOTAL Total Circuit Current ICC (TOTAL) No input signal 23.7 28 37.6 mA Total Circuit Current at Power Save Mode ICC (PS) TOTAL VPS ≤ 0.5 V (Low), No input signal –0.3 10 µA Total Output Power 1 PRFout1VAGC = 2.5 V –15 –11.5 –8 dBm Total Output Power 2 PRFout2VAGC = 1.0 V –56.5 –52 –46.5 dBm LO Carrier Leak LOL fLOL = fLO1 + fLO2 – –40 –30 dBc Image Rejection (Side Band Leak) ImR – –40 –30 dBc I/Q 3rd order distortion IM3 (I/Q) – –50 –30 dBc AGC Gain Control Range GCR VAGC = 2 V → 1 V 35 40 – dB Error Vector Magnitude EVM MOD Pattern: PN9 – 1.2 3.0 %rms Adjacent channel interference Padj ∆f = ±50 kHz, MOD Pattern: PN9 – –65 –60 dBc Spurious suppression Pout (8fLO1) fLO1 × 8, fLO1 × 8 (image)Note – –70 –65 dBc Power Save Rise Time TPS (Rise) VPS (Low) → VPS (High) –2 5 µs Power Save Fall Time TPS (Fall) VPS (High) → VPS (Low) –2 5 µs I/Q input impedance ZI/Q Between pin I/Ib, Q/Qb 80 200 – k Ω I/Q input bias current II/Q Between pin I/Ib, Q/Qb – 5 13 µA LO1 input VSWR ZLO1 fLO1 = 100 M to 300 MHz – 1.5:1 – – Note Without external LC between Fil1 and Fil2 pin on this frequency conditions. Spectrum analyzer conditions: VBW = 300 Hz, RBW = 300 Hz. Remark Electrical characteristics in this document is described for 1.5 GHz system. |
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