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ADV7403 Fiches technique(PDF) 6 Page - Analog Devices |
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ADV7403 Fiches technique(HTML) 6 Page - Analog Devices |
6 / 20 page ADV7403 Data Sheet TIMING CHARACTERISTICS AVDD = 3.15 V to 3.45 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 3.0 V to 3.6 V, PVDD = 1.71 V to 1.89 V. Operating temperature range, unless otherwise noted is TMIN to TMAX: −40°C to +85°C (0°C to 70°C temperature range for ADV7403KSTZ-140). Guaranteed by characterization. Table 3. Parameter Symbol Test Conditions/Comments Min Typ Max Unit SYSTEM CLOCK AND CRYSTAL Crystal Nominal Frequency 28.63636 MHz Crystal Frequency Stability ±50 ppm Horizontal Sync Input Frequency 14.8 110 kHz LLC1 Frequency Range1 12.825 140 MHz I2C PORT2 SCLK Frequency 400 kHz SCLK Minimum Pulse Width High t1 0.6 µs SCLK Minimum Pulse Width Low t2 1.3 µs Hold Time (Start Condition) t3 0.6 µs Setup Time (Start Condition) t4 0.6 µs SDA Setup Time t5 100 ns SCLK and SDA Rise Time t6 300 ns SCLK and SDA Fall Time t7 300 ns Setup Time for Stop Condition t8 0.6 µs RESET FEATURE Reset Pulse Width 5 ms CLOCK OUTPUTS LLC1 Mark Space Ratio t9:t10 45:55 55:45 % duty cycle DATA AND CONTROL OUTPUTS Data Output Transition Time SDR (SDP)3 t11 Negative clock edge to start of valid data 3.6 ns t12 End of valid data to negative clock edge 2.4 ns Data Output Transition Time SDR (CP)4 t13 End of valid data to negative clock edge 2.8 ns t14 Negative clock edge to start of valid data 0.1 ns Data Output Transition Time DDR (CP)4, 5 t15 Positive clock edge to end of valid data −4 + TLLC1/4 ns t16 Positive clock edge to start of valid data 0.25 + TLLC1/4 ns t17 Negative clock edge to end of valid data −2.95 + TLLC1/4 ns t18 Negative clock edge to start of valid data −0.5 + TLLC1/4 ns DATA and CONTROL INPUTS2 Input Setup Time (Digital Input Port) t19 HS_IN, VS_IN 9 ns DE_IN, data inputs 2.2 ns Input Hold Time (Digital Input Port) t20 HS_IN, VS_IN 7 ns DE_IN, data inputs 2 ns 1 Maximum LLC1 frequency is 110 MHz for ADV7403BSTZ-110. 2 TTL input values are 0 V to 3 V with rise/fall times ≥ 3 ns measured between the 10% and 90% points. 3 SDP timing figures obtained using default drive strength value (0xD5) in Subaddress 0xF4. 4 CP timing figures obtained using maximum drive strength value (0xFF) in Subaddress 0xF4. 5 DDR timing specifications dependent on LLC1 output pixel clock; TLCC1/4 = 9.25 ns at LLC1 = 27 MHz. Rev. B | Page 6 of 20 |
Numéro de pièce similaire - ADV7403_15 |
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Description similaire - ADV7403_15 |
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