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ADV7393 Fiches technique(PDF) 4 Page - Analog Devices |
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ADV7393 Fiches technique(HTML) 4 Page - Analog Devices |
4 / 108 page ADV7390/ADV7391/ADV7392/ADV7393 Data Sheet 3/09—Rev. 0 to Rev. A Changes to Features Section............................................................ 1 Deleted Detailed Features Section, Changes to Table 1............... 4 Changes to Figure 1, Added Figure 2............................................. 5 Changes to Table 2, Input Clock Specifications Section, and Analog Output Specifications Section........................................... 6 Changes to Digital Input/Output Specifications—3.3 V Section and Table 5......................................................................................... 7 Added Digital Input/Output Specifications—1.8 V Section and Table 6 ................................................................................................ 7 Changes to MPU Port Timing Specifications Section, Default Conditions ........................................................................... 7 Changes to Digital Timing Specifications—3.3 V Section and Table 8 ................................................................................................ 8 Added Digital Timing Specifications—1.8 V Section and Table 9 ................................................................................................ 9 Added Video Performance Specifications Section, Default Conditions ....................................................................................... 10 Added Power Specifications Section, Default Conditions........ 10 Changes to Table 11........................................................................ 10 Changes to Figure 16...................................................................... 16 Changes to Table 12........................................................................ 17 Changes to Table 14, Pin 19 and Pin 1 Descriptions ................. 18 Changes to MPU Port Description Section ................................ 25 Changes to I2C Operation Section ............................................... 25 Added Table 15 ............................................................................... 25 Changes to Table 17........................................................................ 28 Changes to Table 19, 0x30 Bit Description ................................. 30 Changes to Table 27........................................................................ 37 Changes to Table 29, 0x8B Bit Description................................. 39 Changes to Table 30 ....................................................................... 40 Changes to Table 31 ....................................................................... 41 Added Table 32 ............................................................................... 42 Renamed Features Section to Design Features Section............. 48 Changes to ED/HD Nonstandard Timing Mode Section......... 48 Added the HD Interlace External HSYNC and VSYNC Considerations Section.................................................................. 49 Changes to SD Subcarrier Frequency Lock, Subcarrier Reset, and Timing Reset Section.............................................................. 49 Changes to Subaddress 0x8C to Subaddress 0x8F Section....... 51 Changes to Programming the FSC Section................................... 51 Changes to Subaddress 0x82, Bit 4 Section................................. 51 Added SD Manual CSC Matrix Adjust Feature Section............ 54 Added Table 47 ............................................................................... 55 Changes to Subaddress 0x9C to Subaddress 0x9F Section....... 56 Changes to Subaddress 0xBA Section.......................................... 56 Added Sleep Mode Section ........................................................... 65 Changes to Pixel and Control Port Readback Section .............. 66 Changes to Reset Mechanisms Section ....................................... 66 Added SD Teletext Insertion Section........................................... 66 Added Figure 87 ............................................................................. 67 Added Figure 88 ............................................................................. 68 Changes to DAC Configuration Section..................................... 68 Added Unused Pins Section.......................................................... 68 Changes to Power Supply Sequencing Section........................... 70 Changes to Internal Test Pattern Generation Section ............... 77 Changes to SD Timing, Mode 0 (CCIR-656)—Slave Option (Subaddress 0x8A = XXXXX000) Section.................................. 78 10/06—Revision 0: Initial Version Rev. H | Page 4 of 108 |
Numéro de pièce similaire - ADV7393_15 |
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Description similaire - ADV7393_15 |
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