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ADV7390 Fiches technique(PDF) 7 Page - Analog Devices |
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ADV7390 Fiches technique(HTML) 7 Page - Analog Devices |
7 / 108 page Data Sheet ADV7390/ADV7391/ADV7392/ADV7393 SPECIFICATIONS POWER SUPPLY SPECIFICATIONS All specifications TMIN to TMAX (−40°C to +85°C), unless otherwise noted. Table 3. Parameter Min Typ Max Unit SUPPLY VOLTAGES VDD 1.71 1.8 1.89 V VDD_IO 1.71 3.3 3.63 V PVDD 1.71 1.8 1.89 V VAA 2.6 3.3 3.465 V POWER SUPPLY REJECTION RATIO 0.002 %/% INPUT CLOCK SPECIFICATIONS VDD = 1.71 V to 1.89 V, PVDD = 1.71 V to 1.89 V, VAA = 2.6 V to 3.465 V, VDD_IO = 1.71 V to 3.63 V. All specifications TMIN to TMAX (−40°C to +85°C), unless otherwise noted. Table 4. Parameter Conditions1 Min Typ Max Unit fCLKIN SD/ED 27 MHz ED (at 54 MHz) 54 MHz HD 74.25 MHz CLKIN High Time, t9 40 % of one clock cycle CLKIN Low Time, t10 40 % of one clock cycle CLKIN Peak-to-Peak Jitter Tolerance 2 ±ns 1 SD = standard definition, ED = enhanced definition (525p/625p), HD = high definition. ANALOG OUTPUT SPECIFICATIONS VDD = 1.71 V to 1.89 V, PVDD = 1.71 V to 1.89 V, VAA = 2.6 V to 3.465 V, VDD_IO = 1.71 V to 3.63 V. All specifications TMIN to TMAX (−40°C to +85°C), unless otherwise noted. Table 5. Parameter Conditions Min Typ Max Unit Full-Drive Output Current RSET = 510 Ω, RL = 37.5 Ω 33 34.6 37 mA All DACs enabled RSET = 510 Ω, RL = 37.5 Ω 31.5 33.5 37 mA DAC 1 enabled only1 Low-Drive Output Current RSET = 4.12 kΩ, RL = 300 Ω 4.3 mA DAC-to-DAC Matching DAC 1, DAC 2, DAC 3 2.0 % Output Compliance, VOC 0 1.4 V Output Capacitance, COUT 10 pF Analog Output Delay2 6 ns DAC Analog Output Skew DAC 1, DAC 2, DAC 3 1 ns 1 The recommended method of bringing this value back to the ideal value is by adjusting Register 0x0B to the recommended value of 0x12. 2 Output delay measured from the 50% point of the rising edge of the input clock to the 50% point of the DAC output full-scale transition. Rev. H | Page 7 of 108 |
Numéro de pièce similaire - ADV7390_15 |
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Description similaire - ADV7390_15 |
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