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ADV7341 Fiches technique(PDF) 4 Page - Analog Devices |
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ADV7341 Fiches technique(HTML) 4 Page - Analog Devices |
4 / 108 page ADV7340/ADV7341 Data Sheet Rev. C | Page 4 of 108 REVISION HISTORY 3/12—Rev. B to Rev. C Change to Features Section ............................................................. 1 Deleted Endnote 1 from Table 1..................................................... 5 Added Conditions to Digital Input/Output Specifications—1.8 V Section............................................................................................................. 8 Changes to Pin 48 Description, Table 15..................................... 22 Changes to Table 21........................................................................ 35 Added Register 0x3A to Table 24 .................................................. 38 Changes to Table 29........................................................................ 42 Changes to Subaddress 0x87, Bit 7 = 1 Section .......................... 49 Deleted ED/HD Nontandard Timing Mode Section, Figure 59, Figure 60, Figure 61, and Table 42................................................ 53 Added External Sync Polarity Section ......................................... 54 Deleted Subcarrier Phase Reset (SCR) Mode and Timing Reset (TR) Mode Sections ....................................................................... 54 Renamed SD Subcarrier Frequency Lock, Subcarrier Phase Reset, and Timing Reset Section to SD Subcarrier Frequency Lock Section .................................................................................... 55 Changes to ED/HD Test Patterns Section................................... 82 9/11—Rev. A to Rev. B Changes to MPU Port Description Section ................................ 28 3/09—Rev. 0 to Rev. A Changes to Features Section............................................................ 1 Deleted Detailed Features Section, Changes to Table 1............... 4 Changes to Figure 1.......................................................................... 5 Changes to Table 6............................................................................ 7 Added Digital Input/Output Specifications—1.8 V Section and Table 7 ................................................................................................ 7 Changes to Digital Timing Specifications—3.3 V Section and Table 8 ................................................................................................ 8 Added Table 9.................................................................................... 9 Changes to MPU Port Timing Specifications Section, Default Conditions ......................................................................... 10 Deleted Figure 20............................................................................ 19 Changes to Table 13........................................................................ 20 Changes to Table 15........................................................................ 21 Changes to MPU Port Description Section ................................ 28 Changes to I2C Operation Section ............................................... 28 Added Table 16 ............................................................................... 28 Added Figure 49 ............................................................................. 29 Changes to Table 17 ....................................................................... 30 Changes to Table 18 ....................................................................... 30 Changes to Table 21, 0x30 Bit Description ................................. 34 Added Table 23 ............................................................................... 36 Changes to Table 29 ....................................................................... 41 Changes to Table 30 ....................................................................... 42 Changes to Table 31, 0xA0 Register Name ................................. 44 Changes to Table 32 ....................................................................... 46 Added Table 33 ............................................................................... 46 Added Table 34 ............................................................................... 47 Changes to Standard Definition Only Section ........................... 48 Changes to Figure 57...................................................................... 51 Renamed Features Section to Design Features Section............. 53 Changes to ED/HD Nonstandard Timing Mode Section......... 53 Added HD Interlace External P_HSYNC and P_VSYNC Considerations Section.................................................................. 54 Changes to SD Subcarrier Frequency Lock, Subcarrier Phase Reset, and Timing Reset Section .................................................. 54 Changes to Subaddress 0x8C to Subaddress 0x8F Section....... 56 Changes to Programming the FSC Section................................... 56 Changes to Subaddress 0x82, Bit 4 Section................................. 56 Added SD Manual CSC Matrix Adjust Feature Section............ 59 Changes to Subaddress 0x9C to Subaddress 0x9F Section....... 60 Changes to SD Brightness Detect Section................................... 61 Changes to Figure 71...................................................................... 63 Added Sleep Mode Section ........................................................... 71 Changes to Pixel and Control Port Readback Section .............. 71 Changes to Reset Mechanism Section ......................................... 71 Added SD Teletext Insertion Section........................................... 71 Added Figure 86 and Figure 87 .................................................... 73 Added Unused Pins Section.......................................................... 73 Changes to Power Supply Sequencing Section........................... 75 Changes to Figure 94...................................................................... 78 Changes to SD Wide Screen Signaling Section .......................... 80 Changes to Internal Test Pattern Generation Section ............... 82 Changes to SD Timing, Mode 0 (CCIR-656)—Slave Option (Subaddress 0x8A = XXXXX000) Section.................................. 83 Added Configuration Scripts Section.......................................... 96 10/06—Revision 0: Initial Version |
Numéro de pièce similaire - ADV7341_15 |
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Description similaire - ADV7341_15 |
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