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ADM1041A_15 Datasheet(Fiches technique) 8 Page - Analog Devices

Numéro de pièce ADM1041A_15
Description  Secondary-Side Controller with Current Share and Housekeeping
Télécharger  56 Pages
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Fabricant  AD [Analog Devices]
Site Internet  http://www.analog.com
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ADM1041A
Rev. 0 | Page 8 of 56
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
DC Offset Trim Range (with Respect to Input)
−8
mV
Reg 17h[2:0] = 000. See Table 32 .
−15
mV
Reg 17h[2:0] = 001. See Table 32.
−30
mV
Reg 17h[2:0] = 010. See Table 32.
8
mV
Reg 17h[2:0] = 100. See Table 32.
15
mV
Reg 17h[2:0] = 101. See Table 32.
30
mV
Reg 17h[2:0] = 110. See Table 32.
DC Offset Trim Step Size
30
μV
VCM = 2.0 V, VDIFF = 0 V
(with respect to input)
50
μV
8 bits, 255 steps
120
μV
Reg 15h[7:0]. See Table 30.
CURRENT SENSE CALIBRATION
Total Current Sense Error2
(Gain and Offset)
VCSCM = 2.0V, 0°C ≤ TA ≤ 85°C,
SHRS = SHRO = 2 V. Gain = 230x.
±3
%
Chopper on
±6
%
Chopper off
Gain Range (ISENSE)
Max input voltage range at CS+, CS
Gain Setting 1 (Reg 16h[2:0] = 000)
65
V/V
34 mV – 44.5 mV. Gain = 65×.
Gain Setting 2 (Reg 16h[2:0] = 001)
85
V/V
26 mV – 34 mV. Gain = 85×.
Gain Setting 3 (Reg 16h[2:0] = 010)
110
V/V
20 mV – 26 mV. Gain = 110×.
Gain Setting 4 (Reg 16h[2:0] = 100)
135
V/V
16 mV – 20 mV. Gain = 135×.
Gain Setting 5 (Reg 16h[2:0] = 101)
175
V/V
12 mV – 16 mV. Gain = 175×.
Gain Setting 6 (Reg 16h[2:0] = 110)
230
V/V
9.5 mV – 12 mV. Gain = 230×
Full Scale (No Offset)
2.0
V
VZO = 0
Attenuation Range
65 to 99
%
Reg 06h[7:1]. See Table 15.
Current Share Trim Step (at SHRO)
0.4
%
SHRS = SHRO = 1 V
8
mV
7 bits, 127 steps ISHARE slope
Gain Accuracy2, 4, 40 mV at CS+, CS
−5
+5
%
0 V ≤ VCSCM ≤ 0.3 V. Gain = 65×.
VCSCM = input common mode.
Gain Accuracy2, 4, 20 mV at CS+, CS
−5
±1
+5
%
VCSCM = 2.0 V, 0°C ≤ TA ≤ 85°C.
Gain = 135×
Gain Accuracy2, 4, 40 mV at CS+, CS
−2.5
±0.5
+2.5
%
VCSCM = 2.0 V, 0°C ≤ TA ≤ 85°C.
Gain = 65×
SHARE BUS OFFSET
See Figure 13.
Current Share Offset Range
1.25
V
Reg 17h[7] = 1. See Table 32.
Reg 17h[5] = 1. See Table 32.
Zero Current Offset Trim Step
0 ≤ VTRIM ≤ 1.25 V
0.4
%
8 bits, 255 steps, VCT = 1.0 V
5.5
mV
Reg 05h[7:0]. See Table 14.
CURRENT TRANSFORMER SENSE INPUT, ICT
Reg 17h[7] = 1. See Table 32.
Reg 06h = FEh. See Table 15.
Gain Setting 0
4.5
V/V
Reg 17h[5] = 0, VSHARE = 2 V.
See Table 31
Gain Setting 1
2.57
V/V
Reg 17h[5] = 1. See Table 32.
Reg 15h = 05h, approx 1 μA.
See Table 30. VSHARE = 2 V.
CT Input Sensitivity
0.45
0.5
0.68
V
Gain setting = 4.5
CT Input Sensitivity
0.79
1.0
1.20
V
Gain setting = 2.57
Input Impedance2
20
50
Source Current
2.0
μA
See Current-Transformer Input
Section.
Source Current Step Size
170
nA
15 steps Reg 15h[3:0]. See Table 30.
Reverse Current for Extended SMBus
Addressing (Source Current) 5
3.5
5
7
mA
See Figure 38 and the Absolute
Maximum Ratings section.




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