Moteur de recherche de fiches techniques de composants électroniques
Selected language     French  ▼

Delete All


Preview PDF Download HTML

UPC1934 Datasheet(Fiches technique) 11 Page - NEC

Numéro de pièce UPC1934
Télécharger  20 Pages
Scroll/Zoom Zoom In 100% Zoom Out
Fabricant  NEC [NEC]
Site Internet

UPC1934 Datasheet(HTML) 11 Page - NEC

Zoom Inzoom in Zoom Outzoom out
 11 / 20 page
background image
Data Sheet G13567EJ3V0DS00
µµµµ PC1934
Under Voltage Lock-out Circuit
The under voltage lock-out circuit prevents malfunctioning of the internal circuits when the supply voltage is low, such as
when the supply voltage is first applied, or when the power supply is interrupted. When the voltage is low, the two output
transistors are cut off at the same time.
Error Amplifiers
The circuits of the error amplifiers E/A1 and E/A2 are exactly the same. The first stage of the error amplifier is a P-
channel MOS transistor input. Be careful of the input voltage ranges (the common mode input voltage ranges are all 0 to
0.4 V (TYP.)).
PWM Comparators
The output ON duty is controlled according to the outputs of the error amplifiers and the voltage input to the Dead Time
Control pin.
A triangular waveform is input to the non-inverted pin, and the error amplifier output and Dead Time Control pin voltage
are input to the inverted pins of the PWM comparators. Therefore, the output transistor ON period is the period when the
triangular waveform is higher than the error amplifier output and Dead Time Control pin voltage (refer to Timing Charts).
Timer Latch-Method Short Circuit Protection Circuit
When the converter outputs either a channel or both channels drop, the FB outputs of the error amplifiers of those
outputs go low. If the FB output goes lower than the timer latch input detection voltage (VTH = 0.63 V)), then the output of
the SCP comparator goes low, and Q1 goes off.
When Q1 turns OFF, the constant-current supply charges CDLY via the DLY pin. The DLY pin is internally connected to a
flip-flop. When the DLY pin voltage reaches the UV detection voltage (VUV = 0.8 V (TYP.)), the output Q of the flip-flop goes
low, and the output stage of each channel is latched to OFF (refer to Figure 2-1 Block Diagram).
Make the power supply voltage briefly less than the reset voltage (VCCR, 1.0 V TYP.) to reset the latch circuit when the
short-circuit protection circuit has operated.
Output Circuit
The output circuit has an N-channel open-drain output providing an output withstand voltage of 30 V (absolute maximum
rating), and an output current of 21 mA (absolute maximum rating).

Html Pages

1  2  3  4  5  6  7  8  9  10  11  12  13  14  15  16  17  18  19  20 

Datasheet Download

Lien URL

Privacy Policy
AllDATASHEET vous a-t-il été utile ?   [ DONATE ]  

À propos de Alldatasheet   |   Publicit   |   Contactez-nous   |   Politique de confidentialit   |   Echange de liens   |   Manufacturer List
All Rights Reserved©

Mirror Sites
English :  |   English :  |   Chinese :  |   German :  |   Japanese :
Russian :  |   Korean :  |   Spanish :  |   French :  |   Italian :
Portuguese :  |   Polish :  |   Vietnamese :