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AD9381 Fiches technique(PDF) 4 Page - Analog Devices |
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AD9381 Fiches technique(HTML) 4 Page - Analog Devices |
4 / 44 page AD9381 Rev. 0 | Page 4 of 44 AD9381KSTZ-100 AD9381KSTZ-150 Parameter Test Level Conditions Min Typ Max Min Typ Max Unit IDVDD Supply Current (Typical Pattern)1, 4 V 88 110 110 145 mA IPVDD Supply Current (Typical Pattern)1 V 26 35 30 40 mA Power-Down Supply Current (IPD) VI 130 130 mA AC SPECIFICATIONS Intrapair (+ to −) Differential Input Skew (TDPS) IV 360 ps Channel to Channel Differential Input Skew (TCCS) IV 6 Clock Period Low-to-High Transition Time for Data and Controls (DLHT) IV Output drive = high; CL = 10 pF 900 ps IV Output drive = low; CL = 5 pF 1300 ps Low-to-High Transition Time for DATACK (DLHT) IV Output drive = high; CL = 10 pF 650 ps IV Output drive = low; CL = 5 pF 1200 ps High-to-Low Transition Time for Data and Controls (DHLT) IV Output drive = high; CL = 10 pF 850 ps IV Output drive = low; CL = 5 pF 1250 ps High-to-Low Transition Time for DATACK (DHLT) IV Output drive = high; CL = 10 pF 800 ps IV Output drive = low; CL = 5 pF 1200 ps Clock to Data Skew5 (TSKEW) IV –0.5 +2.0 –0.5 +2.0 ns Duty Cycle, DATACK5 IV 45 50 55 % DATACK Frequency (FCIP) VI 20 150 MHz 1 The typical pattern contains a gray scale area, output drive = high. Worst-case pattern is alternating black and white pixels. 2 The typical pattern contains a gray scale area, output drive = high. 3 Specified current and power values with a worst-case pattern (on/off). 4 DATACK load = 10 pF, data load = 5 pF. 5 Drive strength = high. |
Numéro de pièce similaire - AD9381_15 |
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Description similaire - AD9381_15 |
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