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AD9289 Fiches technique(PDF) 5 Page - Analog Devices |
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AD9289 Fiches technique(HTML) 5 Page - Analog Devices |
5 / 32 page AD9289 Rev. 0 | Page 5 of 32 SWITCHING SPECIFICATIONS AVDD = 3.0 V, DRVDD = 3.0 V, conversion rate = 65 MSPS, 2 V p-p differential input, 1.0 V internal reference, AIN = –0.5 dBFS, unless otherwise noted. Table 4. Parameter Temp Test Level Min Typ Max Unit CLOCK Maximum Clock Rate Full VI 65 MSPS Minimum Clock Rate Full IV 12 MSPS Clock Pulse Width High (tEH) Full VI 6.9 7.7 ns Clock Pulse Width Low (tEL) Full VI 6.9 7.7 ns OUTPUT PARAMETERS Valid Time (tV)1 Full IV 0.5 <1.5 CLK cycles Propagation Delay (tPD) Full VI 6.9 9.0 11.6 ns Rise Time (tR) (20% to 80%) Full V 250 ps Fall Time (tF) (20% to 80%) Full V 250 ps FCO Propagation Delay (tFCO) Full V 9.0 ns DCO Propagation Delay (tCPD) Full V 9.0 ns DCO-to-Data Delay (tDATA) Full VI ±100 ±550 ps DCO-to-FCO Delay (tFRAME) Full VI ±100 ±500 ps Data-to-Data Skew (tDATA-MAX – tDATA-MIN) Full IV ±100 ±250 ps PLL Lock Time (tLOCK) 25°C V 1.8 µs Wake-Up Time 25°C V 7 ms Pipeline Latency Full IV 6 CLK cycles APERTURE Aperture Delay (tA) 25°C V 4.5 ns Aperture Uncertainty (Jitter) 25°C V <1 ps rms OUT-OF-RANGE RECOVERY TIME 25°C V 1 CLK cycles 1 Actual valid time is dependent on the moment when LOCK goes low. TIMING DIAGRAMS LOCK DCO– DCO+ D1– D1+ FCO– FCO+ CLK– AIN CLK+ N-1 N tEH tCPD tDATA tV tFRAME MSB (N-7) D6 (N-7) D5 (N-7) D4 (N-7) D3 (N-7) D2 (N-7) D1 (N-7) LSB (N-7) MSB (N-6) tFCO tPD tEL tA STATIC STATIC STATIC INVALID STATIC STATIC STATIC Figure 2. Timing Diagram |
Numéro de pièce similaire - AD9289_15 |
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Description similaire - AD9289_15 |
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