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AD9288 Fiches technique(PDF) 8 Page - Analog Devices |
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AD9288 Fiches technique(HTML) 8 Page - Analog Devices |
8 / 24 page AD9288 Rev. C | Page 8 of 24 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS GND AINA AINA DFS REFINA REFOUT REFINB S1 S2 AINB AINB GND 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 6 7 8 9 10 11 12 48 47 46 45 44 39 38 37 43 42 41 40 PIN 1 IDENTIFIER NC NC VDD GND GND VD VD NC = NO CONNECT GND GND VDD NC NC AD9288 TOP VIEW (Not to Scale) Figure 5. Pin Configuration Table 3. Pin No. Name Description 1, 12, 16, 27, 29, 32, 34, 45 GND Ground 2 AINA Analog Input for Channel A. 3 AINA Analog Input for Channel A (Complementary). 4 DFS Data Format Select. Offset binary output available if set low. Twos complement output available if set high. 5 REFINA Reference Voltage Input for Channel A. 6 REFOUT Internal Reference Voltage. 7 REFINB Reference Voltage Input for Channel B. 8 S1 User Select 1. Refer to Table 4. Tied with respect to VD. 9 S2 User Select 2. Refer to Table 4. Tied with respect to VD. 10 AINB Analog Input for Channel B (Complementary). 11 AINB Analog Input for Channel B. 13, 30, 31, 48 VD Analog Supply (3 V). 14 ENCB Clock Input for Channel B. 15, 28, 33, 46 VDD Digital Supply (3 V). 17–24 D7B–D0 B Digital Output for Channel B. 25, 26, 35, 36 NC Do Not Connect. 37–44 D0A–D7 A Digital Output for Channel A. 47 ENC A Clock Input for Channel A. |
Numéro de pièce similaire - AD9288_15 |
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Description similaire - AD9288_15 |
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