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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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AD8384 Fiches technique(PDF) 3 Page - Analog Devices |
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AD8384 Fiches technique(HTML) 3 Page - Analog Devices |
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3 / 24 page  AD8384 Rev. 0 | Page 3 of 24 SPECIFICATIONS DecDriver Table 1. @ 25°C, AVCC = 15.5 V, DVCC = 3.3 V, TA MIN = 0°C, TA MAX = 85°C, VRH = 9.5 V, VRL = V1 = V2 = 7 V, unless otherwise noted Parameter Conditions Min Typ Max Unit VIDEO DC PERFORMANCE1 TA MIN to TA MAX VDE DAC Code 450 to 800 –7.5 +7.5 mV VCME DAC Code 450 to 800 –3.5 +3.5 mV VIDEO OUTPUT DYNAMIC PERFORMANCE TA MIN to TA MAX , VO = 5 V Step, CL = 150 pF Data Switching Slew Rate 20% to 80% 460 V/µs Invert Switching Slew Rate 20% to 80% 560 V/µs Data Switching Settling Time to 1% 19 24 ns Data Switching Settling Time to 0.25% 30 50 ns Invert Switching Settling Time to 1% VO = 10 V Step 75 120 ns Invert Switching Settling Time to 0.25% VO = 10 V Step 250 500 ns Invert Switching Overshoot VO = 10 V Step 100 200 mV CLK and Data Feedthrough2 10 mV p-p All-Hostile Crosstalk3 Amplitude 10 mV p-p Glitch Duration 30 ns DAC Transition Glitch Energy DAC Code 511 to 512 0.3 nV-s VIDEO OUTPUT CHARACTERISTICS Output Voltage Swing AVCC – VOH, VOL – AGND 1.1 1.3 V Output Voltage—Grounded Mode 0.25 V Data Switching Delay: t94 50 % of VIDx 10 12 14 ns INV Switching Delay: t105 50 % of VIDx 13 15 17 ns Output Current 100 mA Output Resistance 22 Ω REFERENCE INPUTS V1 Range V2 ≥ (V1-0.25V) 5.25 AVCC – 4 V V2 Range V2 ≥ (V1-0.25V) 5.25 AVCC – 4 V V1 Input Current –3 µA V2 Input Current –14 µA VRL Range VRH ≥ VRL V1 – 0.5 AVCC – 1.3 V VRH Range VRH ≥ VRL VRL AVCC V (VRH–VRL) Range VFS = 2(VRH – VRL) 0 2.75 V VRH Input Resistance To VRL 20 kΩ VRL Bias Current –0.2 µA VRH Input Current 125 µA RESOLUTION Coding Binary 10 Bits 1 VDE = differential error voltage; VCME = common-mode error voltage; VFS = full-scale output voltage = 2 × (VRH – VRL). See the section. Accuracy 2 Measured differentially on two outputs as CLK and DB(0:9) are driven and STSQ and XFR are held LOW. 3 Measured differentially on two outputs as the other four are transitioning by 5 V. Measured for both states of INV. 4 Measured from 50% of rising CLK edge to 50% of output change. Measurement is made for both states of INV. 5 Measured from 50% of rising CLK edge to 50% of output change. Refer to Figure 7 for the definition. |
Numéro de pièce similaire - AD8384_15 |
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Description similaire - AD8384_15 |
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