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CD4515BMS Fiches technique(PDF) 1 Page - Intersil Corporation

No de pièce CD4515BMS
Description  CMOS 4-Bit Latch/4-to-16 Line Decoders
Download  9 Pages
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Fabricant  INTERSIL [Intersil Corporation]
Site Internet  http://www.intersil.com/cda/home
Logo INTERSIL - Intersil Corporation

CD4515BMS Fiches technique(HTML) 1 Page - Intersil Corporation

  CD4515BMS Datasheet HTML 1Page - Intersil Corporation CD4515BMS Datasheet HTML 2Page - Intersil Corporation CD4515BMS Datasheet HTML 3Page - Intersil Corporation CD4515BMS Datasheet HTML 4Page - Intersil Corporation CD4515BMS Datasheet HTML 5Page - Intersil Corporation CD4515BMS Datasheet HTML 6Page - Intersil Corporation CD4515BMS Datasheet HTML 7Page - Intersil Corporation CD4515BMS Datasheet HTML 8Page - Intersil Corporation CD4515BMS Datasheet HTML 9Page - Intersil Corporation  
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7-1188
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
CD4514BMS
CD4515BMS
CMOS 4-Bit
Latch/4-to-16 Line Decoders
File Number
3195
December 1992
Pinout
CD4514BMS, CD4515BMS
TOP VIEW
Functional Diagram
1
2
3
4
5
6
7
8
9
10
11
12
STROBE
DATA 1
DATA 2
S7
S6
S5
S4
S3
S2
S1
S0
VSS
16
17
18
19
20
21
22
23
24
15
14
13
VDD
DATA 4
DATA 3
S10
S11
S9
S15
S12
S13
INHIBIT
S8
S14
INHIBIT
23
11
S0
9S1
10
S2
8S3
7S4
6S5
5S6
4S7
18
S8
17
S9
20
S10
4 TO 16
DECODER
VDD = 24
VSS = 12
19
S11
14
S12
13
S13
16
S14
15
S15
LATCH
A
B
C
D
DATA 1
2
DATA 2
3
DATA 3
21
DATA 4
22
STROBE
1
Features
• High-Voltage Types (20-Volt Rating)
• CD4514BMS Output “High” on Select
• CD4515BMS Output “Low” on Select
• Strobed Input Latch
• Inhibit Control
• 100% Tested for Quiescent Current at 20V
• Maximum Input Current of 1
µA at 18V Over Full Pack-
age Temperature Range; 100nA at 18V and 25oC
• Noise Margin (Full Package-Temperature Range):
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
• 5V, 10V, and 15V Parametric Ratings
• Standardized, Symmetrical Output Characteristics
• Meets all Requirements of JEDEC Tentative Standard
No. 13B, "Standard Specifications for Description of
‘B’ Series CMOS Devices"
Applications
• Digital Multiplexing
• Address Decoding
• Hexadecimal/BCD Decoding
• Program-counter Decoding
• Control Decoder
Description
CD4514BMS and CD4515BMS consist of a 4-bit strobed
latch and a 4-to-16-line decoder. The latches hold the last
input data presented prior to the strobe transition from 1 to 0.
Inhibit
control
allows
all
outputs
to
be
placed
at
0(CD4514BMS) or 1(CD4515BMS) regardless of the state of
the data or strobe inputs.
The decode truth table indicates all combinations of data
inputs and appropriate selected outputs.
These devices are similar to industry types MC14514 and
MC14515.
The CD4514BMS and CD4515BMS are supplied in these 24
lead outline packages:
Braze Seal DIP
H4V
Frit Seal DIP
H1Z
Ceramic Flatpack
H4P


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