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CD40174BMS Fiches technique(PDF) 4 Page - Intersil Corporation |
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CD40174BMS Fiches technique(HTML) 4 Page - Intersil Corporation |
4 / 8 page 7-1387 Specifications CD40174BMS Output Current (Source) IOH15 VDD =15V, VOUT = 13.5V 1, 2 +125oC - -2.4 mA -55oC - -4.2 mA Input Voltage Low VIL VDD = 10V, VOH > 9V, VOL < 1V 1, 2 +25oC, +125oC, -55oC -3 V Input Voltage High VIH VDD = 10V, VOH > 9V, VOL < 1V 1, 2 +25oC, +125oC, -55oC +7 - V Propagation Delay Clock to Output TPHL1 TPLH1 VDD = 10V 1, 2, 3 +25oC - 140 ns VDD = 15V 1, 2, 3 +25oC - 100 ns Propagation Delay CLEAR to Output TPHL2 VDD = 10V 1, 2, 3 +25oC - 100 ns VDD = 15V 1, 2, 3 +25oC - 80 ns Transition Time TTHL TTLH VDD = 10V 1, 2, 3 +25oC - 100 ns VDD = 15V 1, 2, 3 +25oC - 80 ns Maximum Clock Input Frequency FCL VDD = 10V 1, 2, 3 +25oC 6 - MHz VDD = 15V 1, 2, 3 +25oC 8 - MHz Minimum Data Setup Time TS VDD = 5V 1, 2, 3 +25oC - 40 ns VDD = 10V 1, 2, 3 +25oC - 20 ns VDD = 15V 1, 2, 3 +25oC - 10 ns Minimum Data Hold Time TH VDD = 5V 1, 2, 3 +25oC - 80 ns VDD = 10V 1, 2, 3 +25oC - 40 ns VDD = 15V 1, 2, 3 +25oC - 30 ns Minimum Clock Pulse Width TW VDD = 5V 1, 2, 3 +25oC - 130 ns VDD = 10V 1, 2, 3 +25oC - 60 ns VDD = 15V 1, 2, 3 +25oC - 40 ns Maximum Clock Rise and Fall Time TRCL TFCL VDD = 5V 1, 2, 3, 4 +25oC15 - µs VDD = 10V 1, 2, 3, 4 +25oC15 - µs VDD = 15V 1, 2, 3, 4 +25oC15 - µs Minimum CLEAR Removal Time TREM VDD = 5V 1, 2, 3 +25oC- 0 ns VDD = 10V 1, 2, 3 +25oC- 0 ns VDD = 15V 1, 2, 3 +25oC- 0 ns Minimum CLEAR Pulse Width TW VDD = 5V 1, 2, 3 +25oC - 100 ns VDD = 10V 1, 2, 3 +25oC - 50 ns VDD = 15V 1, 2, 3 +25oC - 40 ns Input Capacitance CIN CLEAR 1, 2 +25oC - 40 pF All others 1, 2 +25oC - 7.5 pF NOTES: 1. All voltages referenced to device GND. 2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized on initial design release and upon design changes which would affect these characteristics. 3. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 4. If more than one unit is cascaded, TRCL should be made less than or equal to the sumof the transition time and the fixed propagation delay of the output of the driving stage for the estimated capacitive load. TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE LIMITS UNITS MIN MAX |
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