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CD4014BMS Fiches technique(PDF) 4 Page - Intersil Corporation

No de pièce CD4014BMS
Description  CMOS 8-Stage Static Shift Registers
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Fabricant  INTERSIL [Intersil Corporation]
Site Internet  http://www.intersil.com/cda/home
Logo INTERSIL - Intersil Corporation

CD4014BMS Fiches technique(HTML) 4 Page - Intersil Corporation

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Specifications CD4014BMS, CD4021BMS
Propagation Delay
TPHL
TPLH
VDD = 10V
1, 2, 3
+25oC
-
160
ns
VDD = 15V
1, 2, 3
+25oC
-
120
ns
Transition Time
TTHL
TTLH
VDD = 10V
1, 2, 3
+25oC
-
100
ns
VDD = 15V
1, 2, 3
+25oC
-
80
ns
Maximum Clock Input
Frequency
FCL
VDD = 10V
1, 2, 3
+25oC
6
-
MHz
VDD = 15V
1, 2, 3
+25oC
8.5
-
MHz
Clock Rise and Fall Time
(Note 4)
TRCL
TFCL
VDD = 5V
3, 5
+25oC-
15
µs
VDD = 10V
3, 5
+25oC-
15
µs
VDD = 15V
3, 5
+25oC-
15
µs
Minimum Hold Time Seri-
al In, Parallel In
Parallel/Serial Control
TH
VDD = 5V
1, 2, 3
+25oC-
0
ns
VDD = 10V
1, 2, 3
+25oC-
0
ns
VDD = 15V
1, 2, 3
+25oC-
0
ns
Minimum Clock Pulse
Width
TW
VDD = 5V
1, 2, 3
+25oC
-
180
ns
VDD = 10V
1, 2, 3
+25oC
-
80
ns
VDD = 15V
1, 2, 3
+25oC
-
50
ns
Minimum Setup Time
Serial Input (Ref. to CL)
TS
VDD = 5V
2, 3
+25oC
-
120
ns
VDD = 10V
2, 3
+25oC
-
80
ns
VDD = 15V
2, 3
+25oC
-
60
ns
Minimum Setup Time
Parallel Inputs
CD4014BMS
(Ref. to CL)
TS
VDD = 5V
2, 3
+25oC
-
80
ns
VDD = 10V
2, 3
+25oC
-
50
ns
VDD = 15V
2, 3
+25oC
-
40
ns
Minimum Setup Time
Parallel Inputs
CD4021BMS
(Ref. to P/S)
TS
VDD = 5V
2, 3
+25oC
-
50
ns
VDD = 10V
2, 3
+25oC
-
30
ns
VDD = 15V
2, 3
+25oC
-
20
ns
Minimum Setup Time
Parallel/Serial Control
CD4014BMS (Ref. to CL)
TS
VDD = 5V
2, 3
+25oC
-
180
ns
VDD = 10V
2, 3
+25oC
-
80
ns
VDD = 15V
2, 3
+25oC
-
60
ns
Minimum P/S Pulse
Width (CD4021BMS)
TWH
VDD = 5V
2, 3
+25oC
-
160
ns
VDD = 10V
2, 3
+25oC
-
80
ns
VDD = 15V
2, 3
+25oC
-
50
ns
Minimum P/S Removal
Time CD4021BMS
(Ref. to CL)
TREM
VDD = 5V
2, 3
+25oC
-
280
ns
VDD = 10V
2, 3
+25oC
-
140
ns
VDD = 15V
2, 3
+25oC
-
100
ns
Input Capacitance
CIN
Any Input
1, 2
+25oC
-
7.5
pF
NOTES:
1. All voltages referenced to device GND.
2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized
on initial design release and upon design changes which would affect these characteristics.
3. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
4. If more than one unit is cascaded, TRCL should be made less than or equal to the sum of the transition time and the fixed propagation
delay of the output of the driving stage for the estimated capacitive load.
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
(Continued)
PARAMETER
SYMBOL
CONDITIONS
NOTES
TEMPERATURE
LIMITS
UNITS
MIN
MAX


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