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CD22402D Fiches technique(PDF) 5 Page - Harris Corporation |
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CD22402D Fiches technique(HTML) 5 Page - Harris Corporation |
5 / 11 page 8-44 Logic Diagram Switching Electrical Specifications TA = 25oC and CL = 15pF. Typical Temperature Coefficient for All Values of VDD = 0.3%/oC PARAMETER (NOTE 4) SYMBOL TEST CONDITIONS MIN TYP MAX UNITS VDD (V) Output State Propagation Delay Time (50% to 50%) Low-to-High Level tPLH 5 - 40 80 ns High-to-Low Level tPHL 10 - 20 40 ns Output State Transition Time (10% to 90%) Low-to-High tTLH 5 - 45 90 ns High-to-Low tTHL 10 - 30 60 ns Input Capacitance (Per Input) CI -- 5 - pF NOTE: 4. The characteristics given are defined for unbuffered gate in the CMOS process of the CD22402. R S Q Q 10 20 21 1 23 2 22 24 S R Q Q 6 10K 10K 51pF GENLOCK OSC. + 1M 1N914 HOR. DR 0.001 µF 100pF 1M CRYSTAL 32 TIMES HORIZ. 503.496kHz (NOTE 5) (NOTE 6) HOR. PROCESS BLANKING CLOCK TO COUNTERS VERTICAL DRIVE (VERT. RESET TO FIRST VERT. PULSE) INTEGRATOR GENLOCK SYNC NOTES: 5. Pin 21 high when pin 20 is high (or open). 6. Pin 1 high inhibits clock. FIGURE 1. DETAIL OF THE OSCILLATOR/GENLOCK PORTION OF THE CD22402 CD22402 |
Numéro de pièce similaire - CD22402D |
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Description similaire - CD22402D |
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