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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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AD7719 Fiches technique(PDF) 7 Page - Analog Devices |
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AD7719 Fiches technique(HTML) 7 Page - Analog Devices |
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7 / 40 page  REV. A –7– AD7719 TIMING CHARACTERISTICS1, 2 Limit at TMIN, TMAX Parameter (B Version) Unit Conditions/Comments t1 32.768 kHz typ Crystal Oscillator Frequency t2 50 ns min RESET Pulsewidth Read Operation t3 0 ns min RDY to CS Setup Time t4 0 ns min CS Falling Edge to SCLK Active Edge Setup Time3 t5 4 0 ns min SCLK Active Edge to Data Valid Delay 3 60 ns max DVDD = 4.75 V to 5.25 V 80 ns max DVDD = 2.7 V to 3.6 V t5A 4, 5 0 ns min CS Falling Edge to Data Valid Delay3 60 ns max DVDD = 4.75 V to 5.25 V 80 ns max DVDD = 2.7 V to 3.6 V t6 100 ns min SCLK High Pulsewidth t7 100 ns min SCLK Low Pulsewidth t8 0 ns min CS Rising Edge to SCLK Inactive Edge Hold Time3 t9 6 10 ns min Bus Relinquish Time after SCLK Inactive Edge 3 80 ns max t10 100 ns max SCLK Active Edge to RDY High3, 7 Write Operation t11 0 ns min CS Falling Edge to SCLK Active Edge Setup Time3 t12 30 ns min Data Valid to SCLK Edge Setup Time t13 25 ns min Data Valid to SCLK Edge Hold Time t14 100 ns min SCLK High Pulsewidth t15 100 ns min SCLK Low Pulsewidth t16 0 ns min CS Rising Edge to SCLK Edge Hold Time NOTES 1Sample tested during initial release to ensure compliance. All input signals are specified with t R = tF = 5 ns (10% to 90% of DVDD) and timed from a voltage level of 1.6 V. 2See Figures 2 and 3. 3SCLK active edge is falling edge of SCLK. 4These numbers are measured with the load circuit of Figure 1 and defined as the time required for the output to cross the V OL or VOH limits. 5This specification only comes into play if CS goes low while SCLK is low. It is required primarily for interfacing to DSP machines. 6These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back to remove effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the Timing Characteristics are the true bus relinquish times of the part and as such are independent of external bus loading capacitances. 7 RDY returns high after a read of both ADCs. The same data can be read again, if required, while RDY is high, although care should be taken that subsequent reads do not occur close to the next output update. Specifications subject to change without notice. (AVDD = 2.7 V to 3.6 V or AVDD = 4.75 V to 5.25 V; DVDD = 2.7 V to 3.6 V or DVDD = 4.75 V to 5.25 V; AGND = DGND = 0 V; XTAL = 32.768 kHz; Input Logic 0 = 0 V, Logic 1 = DVDD, unless otherwise noted.) ISINK (1.6mA WITH DVDD = 5V 100 A WITH DVDD = 3V) 1.6V ISOURCE (200 A WITH DVDD = 5V 100 A WITH DVDD = 3V) TO OUTPUT PIN 50pF Figure 1. Load Circuit for Timing Characterization CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7719 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE |
Numéro de pièce similaire - AD7719_15 |
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Description similaire - AD7719_15 |
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