2

Thermal Information

Operating Conditions

Thermal Resistance (Typical, Note 2)

θ

PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

130

SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

140

(SOIC - Lead Tips Only)

Maximum Power Dissipation (Any One Transistor) . . . . . . . 300mW

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the

device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:

1. The collector of each transistor of the CA3054 is isolated from the substrate by an integral diode. The substrate must be connected to a voltage

which is more negative than any collector voltage in order to maintain isolation between transistors and provide for normal transistor action. The

substrate should be maintained at signal (AC) ground by means of a suitable grounding capacitor, to avoid undesired coupling between transistors.

2.

Maximum Voltage Ratings

Maximum

Current Ratings

The following chart gives the range of voltages which can be applied to the terminals listed vertically with respect to the termi-

nals listed horizontally. For example, the voltage range of the vertical Terminal 2 with respect to Terminal 4 is +15V to -5V.

(NOTE 4)

TERM

NO.

13

14

1

2

3

4

6

7

8

9

11

12

5

(NOTE 4)

TERM

NO.

mA

mA

13

0, -20

Note 3

+5, -5

Note 3 +15, -5 Note 3 Note 3 Note 3 Note 3 Note 3

Note 3

Note 3

13

5

0.1

14

Note 3 Note 3 Note 3

+20, 0

Note 3 Note 3 Note 3 Note 3 Note 3

Note 3

+20, 0

14

50

0.1

1

+20, 0

Note 3

+20, 0

Note 3 Note 3 Note 3 Note 3 Note 3

Note 3

+20, 0

1

50

0.1

2

Note 3 +15, -5 Note 3 Note 3 Note 3 Note 3 Note 3

Note 3

Note 3

2

5

0.1

3

+1, -5

Note 3 Note 3 Note 3 Note 3 Note 3

Note 3

Note 3

3

5

0.1

4

Note 3 Note 3 Note 3 Note 3 Note 3

Note 3

Note 3

4

0.1

50

6

0, -20

Note 3

+5, -5

Note 3

+15, -5

Note 3

6

5

0.1

7

Note 3 Note 3 Note 3

Note 3

+20, 0

7

50

0.1

8

+20, 0

Note 3

Note 3

+20, 0

8

50

0.1

9

Note 3

+15, -5

Note 3

9

5

0.1

11

-1, -5

Note 3

11

5

0.1

12

Note 3

12

0.1

50

5

Ref.

Sub-

strate

NOTES:

3. Voltages are not normally applied between these terminals. Voltages appearing between these terminals will be safe

if the specified limits between all other terminals are not exceeded.

4. Terminal No. 10 of CA3054 is not used.

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNIT

DC CHARACTERISTICS

For Each Differential Amplifier

Input Offset Voltage (Figure 8)

-

0.45

5

mV

Input Offset Current (Figure 9)

-

0.3

2

µA

Input Bias Current (Figure 5)

-

10

24

µA

Quiescent Operating Current Ratio

(Figure 5)

-

0.98 to

1.02

--

Temperature Coefficient Magnitude of

Input Offset Voltage (Figure 7)

-

1.1

-

I

C(Q1)

I

C(Q2)

------------------

I

C(Q5)

I

C(Q6)

------------------

or

∆V

IO

∆T

-----------------

CA3054