1

March 1997

82C284

Clock Generator and Ready Interface

for 80C286 Processors

Features

• Generates System Clock for 80C286 Processors

• Generates System Reset Output from Schmitt

Trigger Input

- Improved Hysteresis

• Uses Crystal or External Signal for Frequency Source

• Dynamically Switchable between Two Input

Frequencies

• Provides Local READY and MULTIBUS® READY

Synchronization

• Static CMOS Technology

• Single +5V Power Supply

• Available in 18 Lead CerDIP Package

Description

The Intersil 82C284 is a clock generator/driver which

provides clock signals for 80C286 processors and support

components. It also contains logic to supply READY to the

CPU from either asynchronous or synchronous sources and

synchronous RESET from an asynchronous input with

hysteresis.

Pinout

82C284 (CERDIP)

TOP VIEW

Functional Diagram

Ordering Information

PART NUMBER

TEMP. RANGE

PACKAGE

PKG.

NO.

CD82C284-12

18 Ld CERDIP F18.3

ID82C284-10

18 Ld CERDIP F18.3

ID82C284-12

18 Ld CERDIP F18.3

10

11

12

13

14

15

16

17

18

9

8

7

6

5

4

3

2

1

VCC

S1

S0

NC

PCLK

RESET

RES

ARDYEN

CLK

ARDY

SRDY

SRDYEN

READY

EFI

F/C

X2

X1

GND

RESET

SYNCHRONIZER

RES

X1

X2

EFI

F/C

ARDYEN

ARDY

SRDYEN

SRDY

S1

S0

RESET

CLK

READY

PCLK

XTAL

OSC

MUX

SYNCHRONIZER

READY LOGIC

PCLK GENERATOR

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

http://www.intersil.com or 407-727-9207

File Number

2966.1