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8XC251SA Fiches technique(PDF) 25 Page - Intel Corporation |
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8XC251SA Fiches technique(HTML) 25 Page - Intel Corporation |
25 / 36 page PRELIMINARY 25 8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER 5.3.2 EXTERNAL BUS CYCLES, PAGE MODE Figure 10. External Bus Cycle: Code Fetch (Page Mode) XTAL1 ALE TLHLL † A15:8 D7:0 TRHDZ1 RD#/PSEN# P2 P0/A16/A17 TRHDX TLLRL † TAVLL † TRLDV † TRLAZ TAVRL † TAVDV1 † TAVDV2 † TOSC A4213-02 TLHAX † Instruction In A7:0/A16/A17 D7:0 Instruction In A7:0/A16/A17 Page Miss†† Page Hit†† TAVDV3 † The value of this parameter depends on wait states. See the table of AC characteristics. †† A page hit (i.e., a code fetch to the same 256-byte "page" as the previous code fetch) requires one state (2TOSC); a page miss requires two states (4TOSC). ††† During a sequence of page hits, PSEN# remains low until the end of the last page-hit cycle. TLLAX ††† |
Numéro de pièce similaire - 8XC251SA |
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Description similaire - 8XC251SA |
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