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AD1959 Fiches technique(PDF) 5 Page - Analog Devices

No de pièce AD1959
Description  PLL/Multibit DAC
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Fabricant  AD [Analog Devices]
Site Internet  http://www.analog.com
Logo AD - Analog Devices

AD1959 Fiches technique(HTML) 5 Page - Analog Devices

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AD1959
–5–
PIN FUNCTION DESCRIPTIONS
Pin
Input/Output
Mnemonic
Description
1
I
CCLK
Control Clock Input for Control Data. Control input data must be valid on
the rising edge of CCLK. CCLK may be continuous or gated.
2I
CLATCH
Latch Input for Control Data.
3I
RESET
Reset. The AD1959 is placed in a reset mode when this pin is held LO.
The serial control port registers are reset to their default values. Set HI for
normal operation.
4
I
LRCLK
Left/Right Clock Input for Input Data. Must run continuously.
5
I
BCLK
Bit Clock Input for Input Data. Need not run continuously; may be gated
or used in a burst fashion.
6
I
SDATA
Serial input, MSB first, containing two channels of 16/20/24 bits of two’s-
complement data per channel.
7
I
DVDD
Digital Power Supply Connect to Digital 5 V Supply.
8
I
DGND
Digital Ground.
9
O
SCLK0
33.8688 MHz Clock Output.
10
I/O
MCLK
27 MHz Master Clock Output/256 fS DAC Clock Input.
11
O
XOUT
27 MHz Crystal Oscillator Output.
12
I
XIN
27 MHz Crystal Oscillator/External Clock Input.
13
O
SCLK1
256/384 fS Output.
14
O
SCLK2
512 fS/22.5792 MHz Output.
15
PVDD
PLL Power Supply. Connect to PLL 5 V Supply.
16
PGND
PLL Ground.
17
LF0
PLL0 Loop Filter.
18
LF1
PLL1 Loop Filter.
19
AGND0
Analog Ground.
20
O
OUTR
Right Channel Positive Line Level Analog Output.
21
O
FILTR
Voltage Reference Filter Capacitor Connection. Bypass and decouple the
voltage reference with parallel 10
µF and 0.1 µF capacitors to AGND.
22
I
AGND1
Analog Ground.
23
O
OUTL
Left Channel Line Level Analog Output.
24
AVDD
Analog Power Supply. Connect to Analog 5 V Supply.
25
FILTB
Filter Capacitor Connection, Connect 10
µF Capacitor to AGND.
26
O
ZERO
Zero Flag Output. This pin goes HI when both channels have zero signal
input for more than 1024 L/R Clock Cycles.
27
I
MUTE
Mute. Assert HI to Mute Both Stereo Analog Outputs. Deassert LO for
normal operation.
28
I
CDATA
Serial control input, MSB first, containing 16 bits of unsigned data
per channel.


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