Preliminary Data Sheet M14538EJ1V1DS00

11

MC-4R96CEE6B, 4R96CEE6C

Timing Parameters

The following timing parameters are from the RDRAMs pins, not the RIMM. Please refer to the RDRAM data sheet

(

µPD488448, 488488) for detailed timing diagrams.

Para-

Description

MIN.

MAX.

Units

meter

-845

-745

-653

Row Cycle time of RDRAM banks - the interval between ROWA packets with

ACT commands to the same bank.

28

28

28

—

RAS-asserted time of RDRAM bank - the interval between ROWA packet with ACT

command and next ROWR packet with PRER

20

20

20

Note 2

64

µs

Row Precharge time of RDRAM banks - the interval between ROWR packet with

PRER

bank.

888

—

Precharge-to-precharge time of RDRAM device - the interval between

successive ROWR packets with PRER

same device.

888

—

RAS-to-RAS time of RDRAM device - the interval between successive ROWA

packets with ACT commands to any banks of the same device.

888

—

RAS-to-CAS Delay - the interval from ROWA packet with ACT command to

COLC packet with RD or WR command. Note - the RAS-to-CAS delay seen

in the row and column paths through the RDRAM interface.

977

—

CAS Access delay - the interval from RD command to Q read data. The

888

12

CAS Write Delay - interval from WR command to D write data.

6

6

6

6

CAS-to-CAS time of RDRAM bank - the interval between successive COLC

commands.

444

—

Length of ROWA, ROWR, COLC, COLM or COLX packet.

4

4

4

4

Interval from COLC packet with WR command to COLC packet which causes

retire, and to COLM packet with bytemask.

888

—

The interval (offset) from COLC packet with RDA command, or from COLC

packet with retire command (after WRA automatic precharge), or from COLC

packet with PREC command, or from COLX packet with PREX command to

TPARM register.

444

4

Interval from last COLC packet with RD command to ROWR packet with

PRER.

444

—

Interval from last COLC packet with automatic retire command to ROWR

packet with PRER.

444

—

Notes 1. Or equivalent PREC or PREX command.