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ST3421SRG Fiches technique(PDF) 1 Page - Stanson Technology |
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ST3421SRG Fiches technique(HTML) 1 Page - Stanson Technology |
1 / 6 page ST3421SRG P Channel Enhancement Mode MOSFET -5.0A STANSON TECHNOLOGY 120 Bentley Square, Mountain View, Ca 94040 USA www.stansontech.com ST3421SRG 2013. Rev.1 DESCRIPTION ST3421SRG is the P-Channel logic enhancement mode power field effect transistor which is produced using high cell density, DMOS trench technology. This high density process is especially tailored to minimize on-state resistance. These devices are particularly suited for low voltage application such as cellular phone and notebook computer power management, other battery powered circuits, and low in-line power loss are required. The product is in a very small outline surface mount package. PIN CONFIGURATION SOT-23 1.Gate 2.Source 3.Drain PART MARKING SOT-23 Y: Year Code A: Process Code FEATURE -60V/-5.0A, RDS(ON) = 150m-ohm (Typ.) @VGS = -10V -60V/-2.5A, RDS(ON) = 185m-ohm @VGS = -4.5V Super high density cell design for extremely low RDS(ON) Exceptional on-resistance and maximum DC current capability SOT-23 package design 3 1 2 D G S 3 1 2 21YA |
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