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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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ADC1175CIMTCX Fiches technique(PDF) 4 Page - Texas Instruments |
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ADC1175CIMTCX Fiches technique(HTML) 4 Page - Texas Instruments |
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4 / 29 page  Dn DVDD DVSS 12 DVDD DVSS ADC1175 SNAS012H – JANUARY 2000 – REVISED APRIL 2013 www.ti.com PIN DESCRIPTIONS AND EQUIVALENT CIRCUITS (continued) Pin Symbol Equivalent Circuit Description No. CMOS/TTL compatible digital clock Input. VIN is sampled on 12 CLK the falling edge of CLK input. Conversion data digital Output pins. D0 is the LSB, D7 is the 3 thru D0-D7 MSB. Valid data is output just after the rising edge of the CLK 10 input. These pins are enabled by bringing the OE pin low. Positive digital supply pin. Connect to a clean voltage source of +5V. AVDD and DVDD should have a common source and 13 DVDD be separately bypassed with a 10µF capacitor and a 0.1µF ceramic chip capacitor. See POWER SUPPLY CONSIDERATIONS for more information. This digital supply pin supplies power for the digital output 11 DVDD drivers. This pin should be connected to a supply source in the range of 2.5V to the Pin 13 potential. The ground return for the digital supply. AVSS and DVSS 2, 24 DVSS should be connected together close to the ADC1175. Positive analog supply pin. Connected to a quiet voltage source of +5V. AVDD and DVDD should have a common 14, 15, AVDD source and be separately bypassed with a 10 µF capacitor 18 and a 0.1 µF ceramic chip capacitor. See POWER SUPPLY CONSIDERATIONS for more information. The ground return for the analog supply. AVSS and DVSS 20, 21 AVSS should be connected together close to the ADC1175 package. 4 Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: ADC1175 |
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Description similaire - ADC1175CIMTCX |
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