ADC08100

SNAS060I – JUNE 2000 – REVISED MAY 2013

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Specification Definitions

APERTURE (SAMPLING) DELAY is that time required after the fall of the clock input for the sampling switch to

the clock goes low.

APERTURE JITTER is the variation in aperture delay from sample to sample. Aperture jitter shows up as input

noise.

BOTTOM OFFSET is the difference between the input voltage that just causes the output code to transition to

Zero Scale Error.

CLOCK DUTY CYCLE is the ratio of the time that the clock waveform is at a logic high to the total time of one

clock period.

DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1

LSB. Measured at 100 Msps with a ramp input.

EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE BITS) is another method of specifying Signal-to-Noise

and Distortion Ratio, or SINAD. ENOB is defined as (SINAD – 1.76) / 6.02 and says that the converter is

equivalent to a perfect ADC of this (ENOB) number of bits.

FULL POWER BANDWIDTH is a measure of the frequency at which the reconstructed output fundamental

signal is the full power bandwidth.

is defined as:

where

•

(1)

INTEGRAL NON-LINEARITY (INL) is a measure of the deviation of each individual code from a line drawn from

zero scale (½ LSB below the first code transition) through positive full scale (½ LSB above the last code

transition). The deviation of any given code from this straight line is measured from the center of that code value.

The end point test method is used. Measured at 100 Msps with a ramp input.

INTERMODULATION DISTORTION (IMD) is the creation of additional spectral components as a result of two

sinusoidal frequencies being applied to the ADC input at the same time. It is defined as the ratio of the power in

the second and third order intermodulation products to the power in one of the original frequencies. IMD is

usually expressed in dBFS.

MISSING CODE are those output codes that are skipped and will never appear at the ADC outputs. These

codes cannot be reached with any input value.

OUTPUT DELAY is the time delay after the rising edge of the input clock before the data update is present at the

output pins.

OUTPUT HOLD TIME is the length of time that the output data is valid after the rise of the input clock.

PIPELINE DELAY (LATENCY) is the number of clock cycles between initiation of conversion and when that data

is presented to the output driver stage. New data is available at every clock cycle, but the data lags the

conversion by the Pipeline Delay plus the Output Delay.

SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in dB, of the rms value of the input signal at the output

to the rms value of the sum of all other spectral components below one-half the sampling frequency, not

including harmonics or DC.

SIGNAL TO NOISE PLUS DISTORTION (S/(N+D) or SINAD) is the ratio, expressed in dB, of the rms value of

the input signal at the output to the rms value of all of the other spectral components below half the clock

frequency, including harmonics but excluding D.C.

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