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ADC12138CIWM Fiches technique(PDF) 10 Page - Texas Instruments |
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ADC12138CIWM Fiches technique(HTML) 10 Page - Texas Instruments |
10 / 52 page ADC12130, ADC12132, ADC12138 SNAS098G – MARCH 2000 – REVISED MARCH 2013 www.ti.com AC Electrical Characteristics (continued) The following specifications apply for (V + = V A+ = VD+ = +5V, VREF+ = +4.096V, and fully-differential input with fixed 2.048V common-mode voltage) or (V + = V A+ = VD+ = +3.3V, VREF+ = +2.5V and fully-differential input with fixed 1.250V common- mode voltage), VREF− = 0V, 12-bit + sign conversion mode (1), source impedance for analog inputs, V REF− and VREF+ ≤ 25Ω, fCK = fSK = 5 MHz, and 10 (tCK) acquisition time unless otherwise specified. Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = 25°C. (2) Parameter Test Conditions Typical (3) Limits (4) Units (Limits) 6(tCK) 6(tCK) (min) 7(tCK) (max) 6 Cycles Programmed 1.2 μs (min) 1.4 μs (max) 10(tCK) 10(tCK) (min) 11(tCK) (max) 10 Cycles Programmed 2.0 μs (min) 2.2 μs (max) tA Acquisition Time (5) 18(tCK) 18(tCK) (min) 19(tCK) (max) 18 Cycles Programmed 3.6 μs (min) 3.8 μs (max) 34(tCK) 34(tCK) (min) 35(tCK) (max) 34 Cycles Programmed 6.8 μs (min) 7.0 μs (max) 4944(tCK) 4944(tCK) (max) tCAL Self-Calibration Time 988.8 μs (max) 76(tCK) 76(tCK) (max) tAZ Auto Zero Time 15.2 μs (max) 2(tCK) 2(tCK) (min) 3(tCK) (max) Self-Calibration or Auto Zero tSYNC Synchronization Time from DOR 0.40 μs (min) 0.60 μs (max) DOR High Time when CS is Low 9(tSK) 9(tSK) (max) tDOR Continuously for Read Data and Software 1.8 μs (max) Power Up/Down 8(tSK) 8(tSK) (max) tCONV CONV Valid Data Time 1.6 μs (max) (5) If SCLK and CCLK are driven from the same clock source, then tA is 6, 10, 18 or 34 clock periods minimum and maximum. AC Electrical Characteristics The following specifications apply for (V + = V A+ = VD+ = +5V, VREF+ = +4.096V, and fully-differential input with fixed 2.048V common-mode voltage) or (V + = V A+ = VD+ = +3.3V, VREF+ = +2.5V and fully-differential input with fixed 1.250V common- mode voltage), VREF− = 0V, 12-bit + sign conversion mode (1), source impedance for analog inputs, V REF− and VREF+ ≤ 25Ω, fCK = fSK = 5 MHz, and 10 (tCK) acquisition time unless otherwise specified. Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = 25°C. (2) (Continued) (1) The “12-Bit Conversion of Offset” and “12-Bit Conversion of Full-Scale” modes are intended to test the functionality of the device. Therefore, the output data from these modes are not an indication of the accuracy of a conversion result. (2) Timing specifications are tested at the TTL logic levels, VOL = 0.4V for a falling edge and VOL = 2.4V for a rising edge. TRI-STATE output voltage is forced to 1.4V. 10 Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: ADC12130 ADC12132 ADC12138 |
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