TPS84259 datasheet(3/32 Pages) TI1

No de pièce	TPS84259

Description	4.5-V to 40-V Input, 15-W, Negative Output, Integrated Power Solution

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Fabricant	TI1 [Texas Instruments]

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TPS84259

www.ti.com

SLVSBA0B – AUGUST 2012 – REVISED SEPT 2013

ELECTRICAL CHARACTERISTICS

-40°C

≤ TA ≤ +85°C, VIN = 12 V, VOUT = –5.0 V, IOUT = 2.0A

CIN = 2 x 2.2 µF ceramic, COUT = 2 x 47 µF ceramic (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

IOUT

Output current

Over input voltage and output voltage range

0(1)

2.0(2)

A

VIN

Input voltage range

Over output current range

4.5

40(3)

V

UVLO

VIN Undervoltage lockout

Rising only, RUVLO1 = 174 kΩ, RUVLO2 = 63.4 kΩ

4.5

V

VOUT(adj)

Output voltage adjust range

Over output current range

–3.0

–17(3)

V

Set-point voltage tolerance

TA = 25°C, IOUT = 100 mA

2.0%(4)

Temperature variation

–40°C

≤ TA ≤ +85°C

±0.5%

±1.0%

VOUT

Line regulation

Over input voltage range

±0.1%

Load regulation

From 100 mA to IOUT(max)

±0.4%

Total output voltage variation

Includes set-point, line, load, and temperature variation

3.0%(4)

VOUT = –12 V, IOUT = 1.0 A

85 %

VIN = 24 V

VOUT = –5.0 V, IOUT = 1.0 A

81 %

VOUT = –3.3 V, IOUT = 1.0 A

77 %

η

Efficiency

VIN = 12 V

VOUT = –12 V, IOUT = 0.6 A

86 %

VOUT = –5.0 V, IOUT = 1.0 A

81 %

VOUT = –3.3 V, IOUT = 1.0 A

78 %

Output voltage ripple

20 MHz bandwith, 100 mA

≤ IOUT ≤ IOUT(max)

1%

VOUT

ILIM

Current limit threshold

3.0(5)

A

Recovery time

500

µs

1.0 A/µs load step from 25 to 75%

Transient response

IOUT(max)

VOUT over/undershoot

80

mV

VINH

Inhibit threshold voltage

INH with respect to A_VOUT

1.15

1.25

1.36(6)

V

VINH < 1.15 V

–0.9

μA

IINH

INH Input current

VINH > 1.36 V

–3.8

μA

II(stby)

Input standby current

INH pin to A_VOUT

1.3

4

µA

fSW

Switching frequency

RT pin to A_VOUT

700

800

900

kHz

RRT = 0 Ω

700(7)

900(7)

kHz

fCLK

Synchronization frequency

RRT = 93.1 kΩ

400(7)

600(7)

kHz

VCLK-H

CLK High-Level Threshold

With respect to A_VOUT

1.9

2.2

V

VCLK-L

CLK Low-Level Threshold

With respect to A_VOUT

0.5

0.7

V

DCLK

CLK Duty cycle

25%

50%

75%

Thermal shutdown

180

°C

Thermal Shutdown

Thermal shutdown hysteresis

15

°C

Ceramic

4.7(8)

10

CIN

External input capacitance

µF

Non-ceramic

22

COUT

External output capacitance

100(9)

430(9)

µF

(1)

This device can regulate VOUT down to 0 A, however the ripple may increase due to pulse-skipping at light loads. See Light-Load

Behavior for more information. See No-Load Operation when operating at 0 A.

(2)

The maximum current is dependant on VIN and VOUT, see Figure 35.

(3)

The sum of VIN + |VOUT| must not exceed 50 V.

(4)

The stated limit of the set-point voltage tolerance includes the tolerance of both the internal voltage reference and the internal

adjustment resistor. The overall output voltage tolerance will be affected by the tolerance of the external RSET resistor.

(5)

This product is not designed to endure a sustained (> 5 sec) over-current condition.

(6)

If this pin is left open circuit, the device operates when input power is applied. An external level-shifter is required to interface with this

pin. See Output On/Off Inhibit (INH) for further guidance.

(7)

The synchronization frequency is dependant on VIN and VOUT as shown in Switching Frequency. RRT must be either 0 Ω or 93.1kΩ.

(8)

A minimum of 4.7 µF of ceramic external capacitance is required across the input (VIN and PGND connected) for proper operation.

Locate the capacitor close to the device. See Table 3 for more details.

(9)

The amount of required capacitance must include at least 2 x 47 µF ceramic capacitor (or 4 x 22 µF). Locate the capacitance close to

the device. Adding additional capacitance close to the load improves the response of the regulator to load transients. See Table 3 for

more details. See Inrush Current section when adding additional output capacitance.

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