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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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FM31256 Fiches technique(PDF) 6 Page - Cypress Semiconductor |
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FM31256 Fiches technique(HTML) 6 Page - Cypress Semiconductor |
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6 / 33 page  FM3164/FM31256 Document Number: 001-86391 Rev. *C Page 6 of 33 seconds in 100 ms increments via a 5-bit nonvolatile register. All programmed settings are minimum values and vary with temperature according to the operating specifications. The watchdog has two additional controls associated with its operation, a watchdog enable bit (WDE) and timer restart bits (WR). Both the enable bit must be set and the watchdog must timeout in order to drive RST active. If a reset event occurs, the timer will automatically restart on the rising edge of the reset pulse. If WDE = ‘0’, the watchdog timer runs but a watchdog fault will not cause RST to be asserted LOW. The WTR flag will be set, indicating a watchdog fault. This setting is useful during software development if the developer does not want RST to drive. Note that setting the maximum timeout setting (11111b) disables the counter to save power. The second control is a nibble that restarts the timer preventing a reset. The timer should be restarted after changing the timeout value. The watchdog timeout value is located in register 0Ah, bits 4:0, and the watchdog enable is bit 7. The watchdog is restarted by writing the pattern 1010b to the lower nibble of register 09h. Writing this pattern will also cause the timer to load new timeout values. Writing other patterns to this address will not affect its operation. Note the watchdog timer is free-running. Prior to enabling it, users should restart the timer as described above. This assures that the full timeout period will be set immediately after enabling. The watchdog is disabled when VDD is below VTP. The following table summarizes the watchdog bits. A block diagram follows. Manual Reset The RST is a bi-directional signal allowing the FM3164/FM31256 to filter and de-bounce a manual reset switch. The RST input detects an external low condition and responds by driving the RST signal LOW for 100 ms. Note The internal weak pull-up eliminates the need for additional external components. Reset Flags In case of a reset condition, a flag bit will be set to indicate the source of the reset. A low-VDD reset is indicated by the POR flag, register 09h, bit 6. A watchdog reset is indicated by the WTR flag, register 09h, bit 7. Note that the flags are internally set in response to reset sources, but they must be cleared by the user. When the register is read, it is possible that both flags are set if both have occurred since the user last cleared them. Early Power Fail Comparator An early power fail warning can be provided to the processor well before VDD drops out of spec. The comparator is used to create a power fail interrupt (NMI). This can be accomplished by connecting the PFI pin to the unregulated power supply via a resistor divider. An application circuit is shown below. The voltage on the PFI input pin is compared to an onboard 1.2 V reference. When the PFI input voltage drops below this threshold, the comparator will drive the CAL/PFO pin to a LOW state. The comparator has 100 mV (max) of hysteresis to reduce noise sensitivity, only for a rising PFI signal. For a falling PFI edge, there is no hysteresis. Watchdog Timeout WDT(4:0) 0Ah, bits 4:0 Watchdog Enable WDE 0Ah, bit 7 Watchdog Restart WR(3:0) 09h, bits 3:0 Figure 3. Watchdog Timer Timebase Down Counter Watchdog Timer Settings 100 ms clock WDE RST WR(3:0) = 1010b to restart Figure 4. Manual Reset Figure 5. Comparator as a Power-Fail Warning FM3164/FM31256 Reset Switch RST MCU RST FM3164/FM31256 drives 100 ms (min.) Behavior Switch + - 1.2 V ref Regulator VDD FM3164/ FM31256 CAL/PFO PFI To MCU NMI input |
Numéro de pièce similaire - FM31256 |
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Description similaire - FM31256 |
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