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J112 Fiches technique(PDF) 2 Page - Fairchild Semiconductor

No de pièce J112
Description  This device is designed for low level analog switching, sample and hold circuits and chopper stabilized amplifiers
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Fabricant  FAIRCHILD [Fairchild Semiconductor]
Site Internet  http://www.fairchildsemi.com
Logo FAIRCHILD - Fairchild Semiconductor

J112 Fiches technique(HTML) 2 Page - Fairchild Semiconductor

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© 2012 Fairchild Semiconductor Corporation
www.fairchildsemi.com
J111 / J112 / J113 / MMBFJ111 / MMBFJ112 / MMBFJ112_SB51338 / MMBFJ113
Rev. B0
2
Electrical Characteristics T
a = 25°C unless otherwise noted
* Pulse Test: Pulse Width
 300s, Duty Cycle  3.0%
Typical Performance Characteristics
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Units
Off Characteristics
BV(BR)GSS Gate-Source Breakdown Voltage IG = -1.0A, VDS = 0
-35
V
IGSS
Gate Reverse Current
VGS = -15V, VDS = 0
-1.0
nA
VGS(off)
Gate-Source Cutoff Voltage
VDS = 5.0V, ID = 1.0A
111
112
MMBFJ112_SB51338
113
-3.0
-1.0
-3.0
-0.5
-10
-5.0
-5.0
-3.0
V
V
V
V
ID(off)
Drain Cutoff Leakage Current
VDS = 5.0V, VGS = -10V
1.0
nA
On Characteristics
IDSS
Zero-Gate Voltage Drain
Current*
VDS = 15V, IGS = 0
111
112
113
20
5.0
2.0
mA
mA
mA
rDS(on)
Drain-Source On Resistance
VDS  0.1V, VGS = 0
111
112
113
30
50
100
Small Signal Characteristics
Cdg(on)
Csg(on)
Drain Gate & Source Gate On
Capacitance
VDS = 0, VGS = 0, f = 1.0MHz
28
pF
Cdg(off)
Drain-Gate Off Capacitance
VDS = 0, VGS = -10V, f = 1.0MHz
5.0
pF
Csg(off)
Source-Gate Off Capacitance
VDS = 0, VGS = -10V, f = 1.0MHz
5.0
pF
Parameter Interactions
0.5
1
2
5
10
5
10
20
50
100
5
10
20
50
100
V
- GATE CUTOFF VOLTAGE (V)
GS (OFF)
I
, g
@ V
= 15V,
V
= 0 PULSED
r
@ 1.0 mA, V
= 0
V
@ V
= 15V,
I
= 1.0 nA
GS(off)
DSS
r
D
I
DSS
DS
DS
GS
DS
GS
fs
DS
DS
g
fs
_
_
_
_
_
Common Drain-Source
0
0.4
0.8
1.2
1.6
2
0
2
4
6
8
10
V
- DRAIN-SOURCE VOLTAGE (V)
DS
- 0.4 V
- 1.0 V
- 0.8 V
- 0.2 V
- 0.6 V
V
= 0 V
GS
T = 25°C
TYP V
= - 2.0 V
GS(off)
A
- 1.2 V
- 1.4 V


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