Moteur de recherche de fiches techniques de composants électroniques |
|
CS43122-KS Fiches technique(PDF) 10 Page - Cirrus Logic |
|
CS43122-KS Fiches technique(HTML) 10 Page - Cirrus Logic |
10 / 28 page CS43122 10 SWITCHING CHARACTERISTICS - CONTROL PORT (TA = 25° C; VD = 5.25 V to 3.0 Volts; Inputs: logic 0 = AGND, logic 1 = VD, CL = 30 pF) Notes: 8. Data must be held for sufficient time to bridge the 300 ns transition time of SCL. Parameter Symbol Min Max Unit 2 Wire Mode SCL Clock Frequency fscl -100 KHz RST Rising Edge to Start tirs 500 - ns Bus Free Time Between Transmissions tbuf 4.7 - µs Start Condition Hold Time (prior to first clock pulse) thdst 4.0 - µs Clock Low time tlow 4.7 - µs Clock High Time thigh 4.0 - µs Setup Time for Repeated Start Condition tsust 4.7 - µs SDA Hold Time from SCL Falling (Note 8) thdd 0- µs SDA Setup time to SCL Rising tsud 250 - ns Rise Time of Both SDA and SCL Lines tr -1 µs Fall Time of Both SDA and SCL Lines tf -300 ns Setup Time for Stop Condition tsusp 4.7 - µs t buf t hdst t hdst t low t r t f t hdd t high t sud t sust t susp Stop Start Start Stop Repeated SDA SCL t irs RST Figure 2. 2 Wire Mode Control Port Timing |
Numéro de pièce similaire - CS43122-KS |
|
Description similaire - CS43122-KS |
|
|
Lien URL |
Politique de confidentialité |
ALLDATASHEET.FR |
ALLDATASHEET vous a-t-il été utile ? [ DONATE ] |
À propos de Alldatasheet | Publicité | Contactez-nous | Politique de confidentialité | Echange de liens | Fabricants All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |