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CS4216-KQ Fiches technique(PDF) 10 Page - Cirrus Logic |
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CS4216-KQ Fiches technique(HTML) 10 Page - Cirrus Logic |
10 / 58 page Offset Calibration Both input and output offset voltages are mini- mized by internal calibration. Offset calibration occurs after exiting a reset or power down condi- tion. During calibration, which takes 194 frames, output data from the ADCs will be all zeros, and will be flagged as invalid. Also, the DAC outputs will be muted. After power down mode or power up, RESET should be held low for a minimum of 50 ms to allow the voltage reference to settle. Input Gain and Output Level Setting Input gain is adjustable from 0 dB to +22.5 dB in 1.5 dB steps. In serial modes SM1 and SM2, the output level attenuation is adjustable from 0 dB to -22.5 dB. In serial modes SM3 and SM4, the output level attenuation is adjustable from 0 dB to -46.5 dB. Both input and output gain adjustments are internally made on zero- crossings of the analog signal, to minimize "zipper" noise. The gain change automatically takes effect if a zero crossing does not occur within 512 frames. Muting and the ADC Valid Counter The mute function allows the output channels to be silenced. It is the controlling processor’s re- sponsibility to reduce the signal level to a low value before muting, to avoid an audible click. The outputs should be muted before changing the sample frequency. The serial data stream contains a "Valid Data" indicator for the A/D converters which is false until enough clocks have passed since reset, or low-power (power down mode) operation to have valid A/D data from the filters, i.e., until calibra- tion time plus the full latency of the digital filters has passed. Parallel Digital Input/Output Pins Parallel digital inputs are general purpose pins whose value is reflected in the serial data output stream to the processor. Parallel digital outputs provide a way to control external devices using bits in the serial data input stream. All parallel digital pins, with the exception of DI1 and DO1, are multifunction and are defined by the serial mode selected. Serial modes 1 and 2 define all multifunction pins as general purpose digital in- puts and outputs. In Serial mode 3 only two digital inputs and two digital outputs are avail- able. In serial mode 4 only one digital input and digital output exists. Figure 4 shows when the DI pins are latched, and when the DO pins are up- dated in SM3 and SM4. Reset and Power Down Modes Reset places the CS4216 into a known state and must be held low for at least 50 ms after power- up or a hard power down. Reset must also occur when the codec is in master mode and a change in sample frequency is desired. In reset, the digi- tal outputs are driven low. Reset sets all control data register bits to zero. Hard power down mode may be initiated by bringing the PDN pin low. All analog outputs will be driven to the REFBUF voltage which will then decay to zero. All digital outputs will be driven low and then will go to a high imped- ance state. Minimum power consumption will occur if CLKIN is held low. After leaving the power down state, RESET should be held low for 50 ms to allow the analog voltage reference to settle before calibration is started. SSYNC SCLK DI pins latched DO pins update Start of Frame (SM3) Figure 4. Digital Input/Output Timing CS4216 10 DS83F2 |
Numéro de pièce similaire - CS4216-KQ |
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Description similaire - CS4216-KQ |
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