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CS4202-JQ Fiches technique(PDF) 4 Page - Cirrus Logic |
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CS4202-JQ Fiches technique(HTML) 4 Page - Cirrus Logic |
4 / 68 page CS4202 4 DS549PP1 10.5 Reference Design .......................................................................................................... 53 11. GROUNDING AND LAYOUT .............................................................................................. 54 12. PIN DESCRIPTIONS ........................................................................................................ 56 13. PARAMETER AND TERM DEFINITIONS ............................................................................ 62 14. REFERENCE DESIGN ................................................................................................... 64 15. REFERENCES ...................................................................................................................... 65 16. PACKAGE DIMENSIONS ..................................................................................................... 66 LIST OF FIGURES Figure 1. Power Up Timing............................................................................................................ 10 Figure 2. Codec Ready from Start-up or Fault Condition .............................................................. 10 Figure 3. Clocks ............................................................................................................................ 10 Figure 4. Data Setup and Hold ...................................................................................................... 11 Figure 5. PR4 Powerdown and Warm Reset ................................................................................ 11 Figure 6. Test Mode ...................................................................................................................... 11 Figure 7. AC-link Connections....................................................................................................... 12 Figure 8. CS4202 Mixer Diagram .................................................................................................. 14 Figure 9. AC-link Input and Output Framing.................................................................................. 15 Figure 10. Serial Data Port: Six Channel Circuit ........................................................................... 42 Figure 11. Serial Data Format 0 (I2S) ........................................................................................... 43 Figure 12. Serial Data Format 1 (Left Justified) ............................................................................ 43 Figure 13. Serial Data Format 2 (Right Justified, 20-bit data) ....................................................... 43 Figure 14. Serial Data Format 3 (Right Justified, 16-bit data) ....................................................... 43 Figure 15. S/PDIF Output.............................................................................................................. 44 Figure 16. PLL External Loop Filter............................................................................................... 48 Figure 17. External Crystal ............................................................................................................ 49 Figure 18. Line Input (Replicate for Video and AUX) .................................................................... 50 Figure 19. Differential 1 VRMS CD Input ...................................................................................... 50 Figure 20. Microphone Input ......................................................................................................... 51 Figure 21. PC_BEEP Input............................................................................................................ 51 Figure 22. Modem Connection ...................................................................................................... 51 Figure 23. Line Out and Headphone Out Setup ............................................................................ 52 Figure 24. Line Out/Headphone Out Setup ................................................................................... 52 Figure 25. +5V Analog Voltage Regulator..................................................................................... 53 Figure 26. Conceptual Layout for the CS4202 when in XTAL or OSC Clocking Modes ............... 55 Figure 27. Pin Locations for the CS4202 ...................................................................................... 56 Figure 28. CS4202 Reference Design .......................................................................................... 64 |
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Description similaire - CS4202-JQ |
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