CS51313GD16 datasheet(11/20 Pages) CHERRY

No de pièce	CS51313GD16

Description	Synchronous CPU Buck Controller Capable of Implementing Multiple Linear Regulators

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Fabricant	CHERRY [Cherry Semiconductor Corporation]

Site Internet	http://www.cherrycorp.com/

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Application Information: continued

The CPU VCC(CORE) tolerance can be affected by any or all

of the following reasons:

1) buck regulator output voltage setpoint accuracy;

2) output voltage change due to discharging or charging of

the bulk decoupling capacitors during a load current tran-

sient;

3) output voltage change due to the ESR and ESL of the

bulk and high frequency decoupling capacitors, circuit

traces, and vias;

4) output voltage ripple and noise.

Budgeting the tolerance is left up to the designer who must

take into account all of the above effects and provide a

VCC(CORE) that will meet the specified tolerance at the

CPU’s inputs.

The designer must also ensure that the regulator compo-

nent junction temperatures are kept within the manufac-

turer’s specified ratings at full load and maximum ambient

temperature. As computer motherboards become increas-

ingly complex, regulator size also becomes important, as

there is less space available for the CPU power supply.

Step 2: Selection of the Output Capacitors

These components must be selected and placed carefully to

yield optimal results. Capacitors should be chosen to pro-

vide acceptable ripple on the regulator output voltage. Key

specifications for output capacitors are their ESR

(Equivalent Series Resistance), and ESL (Equivalent Series

Inductance). For best transient response, a combination of

low value/high frequency and bulk capacitors placed close

to the load will be required.

In order to determine the number of output capacitors the

maximum voltage transient allowed during load transi-

tions has to be specified. The output capacitors must hold

the output voltage within these limits since the inductor

current can not change with the required slew rate. The

output capacitors must therefore have a very low ESL and

ESR.

The voltage change during the load current transient is:

∆VOUT = ∆IOUT ×

( +ESR+ ),

where

∆IOUT / ∆t = load current slew rate;

∆IOUT = load transient;

∆t = load transient duration time;

ESL = Maximum allowable ESL including capacitors,

circuit traces, and vias;

ESR = Maximum allowable ESR including capacitors

and circuit traces;

tTR = output voltage transient response time.

The designer has to independently assign values for the

change in output voltage due to ESR, ESL, and output

capacitor discharging or charging. Empirical data indicates

that most of the output voltage change (droop or spike

depending on the load current transition) results from the

total output capacitor ESR.

The maximum allowable ESR can then be determined

according to the formula

ESRMAX =

,

where ∆VESR = change in output voltage due to ESR

(assigned by the designer).

Once the maximum allowable ESR is determined, the

number of output capacitors can be found by using the for-

mula

Number of capacitors =

,

where

ESRCAP = maximum ESR per capacitor (specified in

manufacturer’s data sheet);

ESRMAX = maximum allowable ESR.

The actual output voltage deviation due to ESR can then be

verified and compared to the value assigned by the design-

er:

∆VESR = ∆IOUT × ESRMAX

Similarly, the maximum allowable ESL is calculated from

the following formula:

ESLMAX =

,

where

∆I/∆T = load current slew rate (as high as 20A/µs);

∆VESL = change in output voltage due to ESL.

The actual maximum allowable ESL can be determined by

using the equation:

ESLMAX =

,

where ESLCAP = maximum ESL per capacitor (it is estimat-

ed that a 10 × 12mm Aluminum Electrolytic capacitor has

approximately 4nH of package inductance).

The actual output voltage deviation due to the actual maxi-

mum ESL can then be verified:

∆VESL =

.

The designer now must determine the change in output

voltage due to output capacitor discharge during the tran-

sient:

∆VCAP =

,

where

∆tTR = the output voltage transient response time

(assigned by the designer);

∆VCAP = output voltage deviation due to output capaci-

tor discharge;

∆I = Load step.

∆I × ∆tTR

COUT

ESLMAX × ∆I

∆t

ESLCAP

Number of output capacitors

∆VESL × ∆t

∆I

ESRCAP

ESRMAX

∆VESR

∆IOUT

tTR

COUT

ESL

∆t

11

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