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CS51033YDR8 Fiches technique(PDF) 4 Page - Cherry Semiconductor Corporation |
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CS51033YDR8 Fiches technique(HTML) 4 Page - Cherry Semiconductor Corporation |
4 / 8 page 4 Block Diagram G5 COSC CS VCC VC VGATE PGnd VFB Gnd R S 2.5V 1.5V 1.25V 1.15V Q F2 G2 G1 A1 A6 RG VCC A3 2.4V G3 A2 2.5V 1.5V IC 7IC VCC + - IT + Q IT 5 IT 55 G4 Fault Comp + - + - A4 0.7V 2.3V Q R Q S F1 Slow Discharge Comparator Slow Discharge Flip-Flop CS Charge Sense Comparator CS Comparator Oscillator Comparator VFB Comparator VGATE Flip-Flop Hold Off Comp Control Scheme The CS51033 monitors the output voltage to determine when to turn on the PFET. If VFB falls below the internal ref- erence voltage of 1.25V during the oscillator’s charge cycle, the PFET is turned on and remains on for the duration of the charge time. The PFET gets turned off and remains off dur- ing the oscillator’s discharge cycle time with the maximum duty cycle to 80%. It requires 7mV typical, and 20mV maxi- mum ripple on the VFB pin is required to operate. This method of control does not require any loop stability com- pensation. Startup The CS51033 has an externally programmable soft start fea- ture that allows the output voltage to come up slowly, pre- venting voltage overshoot on the output. At startup, the voltage on all pins is zero. As VCC rises, the VC voltage along with the internal resistor RG keeps the PFET off. As VCC and VC continue to rise, the oscillator capacitor (COSC ) and the Soft start/Fault Timing capacitor (CS) charges via internal current sources. COSC gets charged by the current source IC and CS gets charged by the IT source combination described by: ICS = IT - ( + ) The internal Holdoff Comparator ensures that the external PFET is off until VCS > 0.7V preventing the GATE flip-flop (F2) from being set. This allows the oscillator to reach its operating frequency before enabling the drive output. Soft start is obtained by clamping the VFB comparator’s (A6) ref- erence input to approximately 1/2 of the voltage at the CS pin during startup, permitting the control loop and the out- put voltage to slowly increase. Once the CS pin charges above the Holdoff Comparator trip point of 0.7V, the low IT 5 IT 55 Theory of Operation Circuit Description Figure 1: Block Diagram for CS51033 |
Numéro de pièce similaire - CS51033YDR8 |
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Description similaire - CS51033YDR8 |
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