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AD421BRZRL Fiches technique(PDF) 8 Page - Analog Devices |
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AD421BRZRL Fiches technique(HTML) 8 Page - Analog Devices |
8 / 14 page AD421 –8– REV. C WORD "N" 01 10 0 11 0 0 0 00 0 0 0 00 CLOCK DATA LATCH XX X X X X X Figure 7. Write Cycle for Programming Alarm Current Data MICROPROCESSOR INTERFACING AD421 – MC68HC11 (SPI BUS) INTERFACE Figure 8 shows a typical interface between the AD421 and the Motorola MC68HC11 SPI (Serial Peripheral Interface) bus. The SCK, MOSI and SS pins of the 68HC11 are respectively connected to the CLOCK, DATA IN and LATCH pins of the AD421. SCK MOSI SS CLOCK DATA IN LATCH AD421* 68HC11 * ADDITIONAL PINS OMITTED FOR CLARITY Figure 8. AD421 to 68HC11 Interface A typical routine such as the one shown below begins by initializ- ing the state of the various SPI data and control registers. INIT LDAA #$2F ; SS = 1; SCK = 0; MOSI = 1 STAA PORTD ;SEND TO SPI OUTPUTS LDAA #$38 ; SS, SCK, MOSI = OUTPUTS STAA DDRD ;SEND DATA DIRECTION INFO LDAA #$50 ;DABL INTRPTS, SPI IS MASTER & ON STAA SPCR ;CPOL = 0, CPHA = 0, 1MHZ BAUDRATE NEXTPT LDAA MSBY ;LOAD ACCUM W/UPPER 8 BITS BSR SENDAT ;JUMP TO DAC OUTPUT ROUTINE JMP NEXTPT ;INFINITE LOOP SENDAT LDY #$1000 ;POINT AT ON-CHIP REGISTERS BCLR $08,Y,$20 ;DRIVE SS (LATCH) LOW STAA SPDR ;SEND MS-BYTE TO SPI DATA REG WAIT1 LDAA SPSR ;CHECK STATUS OF SPIE BPL WAIT1 ;POLL FOR END OF X-MISSION LDAA LSBY ;GET LOW 8 BITS FROM MEMORY STAA SPDR ;SEND LS-BYTE TO SPI DATA REG WAIT2 LDAA SPSR ;CHECK STATUS OF SPIE BPL WAIT2; ;POLL FOR END OF X-MISSION BSET $08,Y,$20 ;DRIVE SS HIGH TO LATCH DATA RTS The SPI data port is configured to process data in 8-bit bytes. The most significant data byte (MSBY) is retrieved from memory and processed by the SENDAT routine. The SS pin is driven low by indexing into the PORTD data register and clear Bit 5. The MSBY is then sent to the SPI data register where it is automatically transferred to the AD421 internal shift resistor. of 11.147 mA. With 16 clock pulses between consecutive latch signals data written is for normal 4 mA to 20 mA operation. Table II. Ideal Input/Output Code Table for 4 mA to 20 mA Operation Code Output Current 0000 0000 0000 0000 4 mA 0000 0000 0000 0001 4.000244 mA 0000 0000 0000 0010 4.000488 mA 0100 0000 0000 0000 8 mA 1000 0000 0000 0000 12 mA 1100 0000 0000 0000 16 mA 1111 1111 1111 1101 19.999268 mA 1111 1111 1111 1110 19.999512 mA 1111 1111 1111 1111 19.999756 mA WORD "N" WORD "N +1" 10 1 1 1 1 11 1 1 00 0 0 0 0 10 0 1 CLOCK DATA LATCH Figure 6. Write Cycle for 4 mA to 20 mA Operation Alarm Current Coding Table III shows the ideal input-code-to-output-current relation- ship for alarm current programming of the AD421. In this case, the equivalent span is 0 mA to 32 mA but a reliable operating span is 3.5 mA to 24 mA. The part may give an indeterminate output for code values outside the range given in the table. As a result, the user is advised to restrict the code programmed to the part in alarm current mode to within the range shown in Table III. Figure 7 shows a timing diagram for loading an alarm cur- rent of 3.75 mA to the AD421 with an 8-bit microcontroller using three 8-bit writes. The output current values shown assume a REF IN voltage of +2.5 V. With a REF IN of +2.5 V, an ideal 1 LSB = 32 mA/ 131,072 = 244 nA. Table III. Ideal Input/Output Code Table for Alarm Current Operation Code Output Current 0 0011 1000 0000 0000 3.5 mA 0 0011 1100 0000 0000 3.75 mA 0 0100 0000 0000 0000 4 mA 0 1000 0000 0000 0000 8 mA 1 0000 0000 0000 0000 16 mA 1 0100 0000 0000 0000 20 mA 1 0110 0000 0000 0000 22 mA 1 1000 0000 0000 0000 24 mA |
Numéro de pièce similaire - AD421BRZRL |
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Description similaire - AD421BRZRL |
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